581 lines
20 KiB
C++
581 lines
20 KiB
C++
/*
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* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_X86_VM_NATIVEINST_X86_HPP
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#define CPU_X86_VM_NATIVEINST_X86_HPP
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#include "asm/assembler.hpp"
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#include "memory/allocation.hpp"
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#include "runtime/icache.hpp"
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#include "runtime/os.hpp"
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#include "utilities/top.hpp"
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// We have interfaces for the following instructions:
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// - NativeInstruction
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// - - NativeCall
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// - - NativeMovConstReg
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// - - NativeMovConstRegPatching
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// - - NativeMovRegMem
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// - - NativeMovRegMemPatching
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// - - NativeJump
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// - - NativeIllegalOpCode
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// - - NativeGeneralJump
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// - - NativeReturn
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// - - NativeReturnX (return with argument)
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// - - NativePushConst
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// - - NativeTstRegMem
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// The base class for different kinds of native instruction abstractions.
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// Provides the primitive operations to manipulate code relative to this.
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class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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friend class Relocation;
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public:
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enum Intel_specific_constants {
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nop_instruction_code = 0x90,
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nop_instruction_size = 1
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};
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bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
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bool is_dtrace_trap();
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inline bool is_call();
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inline bool is_illegal();
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inline bool is_return();
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inline bool is_jump();
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inline bool is_cond_jump();
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inline bool is_safepoint_poll();
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inline bool is_mov_literal64();
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protected:
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address addr_at(int offset) const { return address(this) + offset; }
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s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
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u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
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jint int_at(int offset) const { return *(jint*) addr_at(offset); }
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intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
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oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
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void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); }
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void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); }
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void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); }
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void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); }
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// This doesn't really do anything on Intel, but it is the place where
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// cache invalidation belongs, generically:
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void wrote(int offset);
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public:
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// unit test stuff
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static void test() {} // override for testing
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inline friend NativeInstruction* nativeInstruction_at(address address);
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};
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inline NativeInstruction* nativeInstruction_at(address address) {
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NativeInstruction* inst = (NativeInstruction*)address;
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#ifdef ASSERT
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//inst->verify();
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#endif
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return inst;
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}
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inline NativeCall* nativeCall_at(address address);
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// The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
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// instructions (used to manipulate inline caches, primitive & dll calls, etc.).
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class NativeCall: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0xE8,
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instruction_size = 5,
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instruction_offset = 0,
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displacement_offset = 1,
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return_address_offset = 5
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};
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enum { cache_line_size = BytesPerWord }; // conservative estimate!
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address instruction_address() const { return addr_at(instruction_offset); }
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address next_instruction_address() const { return addr_at(return_address_offset); }
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int displacement() const { return (jint) int_at(displacement_offset); }
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address displacement_address() const { return addr_at(displacement_offset); }
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address return_address() const { return addr_at(return_address_offset); }
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address destination() const;
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void set_destination(address dest) {
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#ifdef AMD64
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assert((labs((intptr_t) dest - (intptr_t) return_address()) &
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0xFFFFFFFF00000000) == 0,
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"must be 32bit offset");
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#endif // AMD64
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set_int_at(displacement_offset, dest - return_address());
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}
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void set_destination_mt_safe(address dest);
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void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
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void verify();
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void print();
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// Creation
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inline friend NativeCall* nativeCall_at(address address);
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inline friend NativeCall* nativeCall_before(address return_address);
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static bool is_call_at(address instr) {
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return ((*instr) & 0xFF) == NativeCall::instruction_code;
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}
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static bool is_call_before(address return_address) {
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return is_call_at(return_address - NativeCall::return_address_offset);
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}
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static bool is_call_to(address instr, address target) {
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return nativeInstruction_at(instr)->is_call() &&
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nativeCall_at(instr)->destination() == target;
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}
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// MT-safe patching of a call instruction.
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static void insert(address code_pos, address entry);
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static void replace_mt_safe(address instr_addr, address code_buffer);
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};
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inline NativeCall* nativeCall_at(address address) {
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NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
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#ifdef ASSERT
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call->verify();
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#endif
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return call;
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}
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inline NativeCall* nativeCall_before(address return_address) {
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NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
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#ifdef ASSERT
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call->verify();
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#endif
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return call;
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}
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// An interface for accessing/manipulating native mov reg, imm32 instructions.
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// (used to manipulate inlined 32bit data dll calls, etc.)
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class NativeMovConstReg: public NativeInstruction {
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#ifdef AMD64
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static const bool has_rex = true;
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static const int rex_size = 1;
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#else
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static const bool has_rex = false;
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static const int rex_size = 0;
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#endif // AMD64
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public:
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enum Intel_specific_constants {
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instruction_code = 0xB8,
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instruction_size = 1 + rex_size + wordSize,
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instruction_offset = 0,
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data_offset = 1 + rex_size,
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next_instruction_offset = instruction_size,
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register_mask = 0x07
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};
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address instruction_address() const { return addr_at(instruction_offset); }
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address next_instruction_address() const { return addr_at(next_instruction_offset); }
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intptr_t data() const { return ptr_at(data_offset); }
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void set_data(intptr_t x) { set_ptr_at(data_offset, x); }
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void verify();
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void print();
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// unit test stuff
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static void test() {}
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// Creation
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inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
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inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
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};
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inline NativeMovConstReg* nativeMovConstReg_at(address address) {
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NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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inline NativeMovConstReg* nativeMovConstReg_before(address address) {
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NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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class NativeMovConstRegPatching: public NativeMovConstReg {
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private:
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friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
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NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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};
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// An interface for accessing/manipulating native moves of the form:
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// mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
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// mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
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// mov[s/z]x[w/b/q] [reg + offset], reg
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// fld_s [reg+offset]
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// fld_d [reg+offset]
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// fstp_s [reg + offset]
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// fstp_d [reg + offset]
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// mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
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//
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// Warning: These routines must be able to handle any instruction sequences
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// that are generated as a result of the load/store byte,word,long
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// macros. For example: The load_unsigned_byte instruction generates
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// an xor reg,reg inst prior to generating the movb instruction. This
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// class must skip the xor instruction.
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class NativeMovRegMem: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_prefix_wide_lo = Assembler::REX,
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instruction_prefix_wide_hi = Assembler::REX_WRXB,
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instruction_code_xor = 0x33,
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instruction_extended_prefix = 0x0F,
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instruction_code_mem2reg_movslq = 0x63,
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instruction_code_mem2reg_movzxb = 0xB6,
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instruction_code_mem2reg_movsxb = 0xBE,
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instruction_code_mem2reg_movzxw = 0xB7,
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instruction_code_mem2reg_movsxw = 0xBF,
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instruction_operandsize_prefix = 0x66,
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instruction_code_reg2mem = 0x89,
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instruction_code_mem2reg = 0x8b,
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instruction_code_reg2memb = 0x88,
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instruction_code_mem2regb = 0x8a,
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instruction_code_float_s = 0xd9,
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instruction_code_float_d = 0xdd,
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instruction_code_long_volatile = 0xdf,
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instruction_code_xmm_ss_prefix = 0xf3,
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instruction_code_xmm_sd_prefix = 0xf2,
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instruction_code_xmm_code = 0x0f,
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instruction_code_xmm_load = 0x10,
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instruction_code_xmm_store = 0x11,
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instruction_code_xmm_lpd = 0x12,
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instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes,
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instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes,
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instruction_size = 4,
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instruction_offset = 0,
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data_offset = 2,
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next_instruction_offset = 4
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};
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// helper
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int instruction_start() const;
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address instruction_address() const;
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address next_instruction_address() const;
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int offset() const;
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void set_offset(int x);
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void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
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void verify();
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void print ();
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// unit test stuff
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static void test() {}
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private:
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inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
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};
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inline NativeMovRegMem* nativeMovRegMem_at (address address) {
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NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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class NativeMovRegMemPatching: public NativeMovRegMem {
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private:
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friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
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NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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};
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// An interface for accessing/manipulating native leal instruction of form:
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// leal reg, [reg + offset]
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class NativeLoadAddress: public NativeMovRegMem {
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#ifdef AMD64
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static const bool has_rex = true;
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static const int rex_size = 1;
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#else
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static const bool has_rex = false;
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static const int rex_size = 0;
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#endif // AMD64
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public:
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enum Intel_specific_constants {
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instruction_prefix_wide = Assembler::REX_W,
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instruction_prefix_wide_extended = Assembler::REX_WB,
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lea_instruction_code = 0x8D,
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mov64_instruction_code = 0xB8
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};
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void verify();
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void print ();
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// unit test stuff
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static void test() {}
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private:
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friend NativeLoadAddress* nativeLoadAddress_at (address address) {
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NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
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#ifdef ASSERT
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test->verify();
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#endif
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return test;
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}
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};
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// jump rel32off
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class NativeJump: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0xe9,
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instruction_size = 5,
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instruction_offset = 0,
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data_offset = 1,
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next_instruction_offset = 5
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};
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address instruction_address() const { return addr_at(instruction_offset); }
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address next_instruction_address() const { return addr_at(next_instruction_offset); }
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address jump_destination() const {
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address dest = (int_at(data_offset)+next_instruction_address());
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// 32bit used to encode unresolved jmp as jmp -1
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// 64bit can't produce this so it used jump to self.
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// Now 32bit and 64bit use jump to self as the unresolved address
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// which the inline cache code (and relocs) know about
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// return -1 if jump to self
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dest = (dest == (address) this) ? (address) -1 : dest;
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return dest;
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}
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void set_jump_destination(address dest) {
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intptr_t val = dest - next_instruction_address();
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if (dest == (address) -1) {
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val = -5; // jump to self
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}
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#ifdef AMD64
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assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
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#endif // AMD64
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set_int_at(data_offset, (jint)val);
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}
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// Creation
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inline friend NativeJump* nativeJump_at(address address);
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void verify();
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// Unit testing stuff
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static void test() {}
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// Insertion of native jump instruction
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static void insert(address code_pos, address entry);
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// MT-safe insertion of native jump at verified method entry
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static void check_verified_entry_alignment(address entry, address verified_entry);
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static void patch_verified_entry(address entry, address verified_entry, address dest);
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};
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inline NativeJump* nativeJump_at(address address) {
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NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
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#ifdef ASSERT
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jump->verify();
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#endif
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return jump;
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}
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// Handles all kinds of jump on Intel. Long/far, conditional/unconditional
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class NativeGeneralJump: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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// Constants does not apply, since the lengths and offsets depends on the actual jump
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// used
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// Instruction codes:
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// Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off)
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// Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off)
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unconditional_long_jump = 0xe9,
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unconditional_short_jump = 0xeb,
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instruction_size = 5
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};
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address instruction_address() const { return addr_at(0); }
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address jump_destination() const;
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// Creation
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inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
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// Insertion of native general jump instruction
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static void insert_unconditional(address code_pos, address entry);
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static void replace_mt_safe(address instr_addr, address code_buffer);
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void verify();
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};
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inline NativeGeneralJump* nativeGeneralJump_at(address address) {
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NativeGeneralJump* jump = (NativeGeneralJump*)(address);
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debug_only(jump->verify();)
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return jump;
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}
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class NativePopReg : public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0x58,
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instruction_size = 1,
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instruction_offset = 0,
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data_offset = 1,
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next_instruction_offset = 1
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};
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// Insert a pop instruction
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static void insert(address code_pos, Register reg);
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};
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class NativeIllegalInstruction: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B
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instruction_size = 2,
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instruction_offset = 0,
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next_instruction_offset = 2
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};
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// Insert illegal opcode as specific address
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static void insert(address code_pos);
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};
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// return instruction that does not pop values of the stack
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class NativeReturn: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0xC3,
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instruction_size = 1,
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instruction_offset = 0,
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next_instruction_offset = 1
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};
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};
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// return instruction that does pop values of the stack
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class NativeReturnX: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_code = 0xC2,
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instruction_size = 2,
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instruction_offset = 0,
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next_instruction_offset = 2
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};
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};
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// Simple test vs memory
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class NativeTstRegMem: public NativeInstruction {
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public:
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enum Intel_specific_constants {
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instruction_rex_prefix_mask = 0xF0,
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instruction_rex_prefix = Assembler::REX,
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instruction_code_memXregl = 0x85,
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modrm_mask = 0x38, // select reg from the ModRM byte
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modrm_reg = 0x00 // rax
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};
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};
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inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
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inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
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inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
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ubyte_at(0) == NativeReturnX::instruction_code; }
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inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
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ubyte_at(0) == 0xEB; /* short jump */ }
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inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
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(ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
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inline bool NativeInstruction::is_safepoint_poll() {
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#ifdef AMD64
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if (Assembler::is_polling_page_far()) {
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// two cases, depending on the choice of the base register in the address.
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if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix &&
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ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl &&
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(ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) ||
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ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
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(ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) {
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return true;
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} else {
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return false;
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}
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} else {
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if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
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ubyte_at(1) == 0x05) { // 00 rax 101
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address fault = addr_at(6) + int_at(2);
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return os::is_poll_address(fault);
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} else {
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return false;
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}
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}
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#else
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return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
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ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
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(ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
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(os::is_poll_address((address)int_at(2)));
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#endif // AMD64
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}
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inline bool NativeInstruction::is_mov_literal64() {
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#ifdef AMD64
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return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
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(ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
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#else
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return false;
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#endif // AMD64
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}
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#endif // CPU_X86_VM_NATIVEINST_X86_HPP
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