605 lines
20 KiB
C++
605 lines
20 KiB
C++
/*
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* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "memory/resourceArea.hpp"
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#include "nativeInst_x86.hpp"
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#include "oops/oop.inline.hpp"
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#include "runtime/handles.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "utilities/ostream.hpp"
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#ifdef COMPILER1
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#include "c1/c1_Runtime1.hpp"
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#endif
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PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
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void NativeInstruction::wrote(int offset) {
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ICache::invalidate_word(addr_at(offset));
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}
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void NativeCall::verify() {
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// Make sure code pattern is actually a call imm32 instruction.
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int inst = ubyte_at(0);
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if (inst != instruction_code) {
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tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),
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inst);
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fatal("not a call disp32");
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}
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}
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address NativeCall::destination() const {
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// Getting the destination of a call isn't safe because that call can
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// be getting patched while you're calling this. There's only special
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// places where this can be called but not automatically verifiable by
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// checking which locks are held. The solution is true atomic patching
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// on x86, nyi.
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return return_address() + displacement();
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}
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void NativeCall::print() {
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tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
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instruction_address(), destination());
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}
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// Inserts a native call instruction at a given pc
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void NativeCall::insert(address code_pos, address entry) {
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intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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#ifdef AMD64
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guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
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#endif // AMD64
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*code_pos = instruction_code;
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*((int32_t *)(code_pos+1)) = (int32_t) disp;
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ICache::invalidate_range(code_pos, instruction_size);
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}
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// MT-safe patching of a call instruction.
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// First patches first word of instruction to two jmp's that jmps to them
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// selfs (spinlock). Then patches the last byte, and then atomicly replaces
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// the jmp's with the first 4 byte of the new instruction.
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void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
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assert(Patching_lock->is_locked() ||
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SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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assert (instr_addr != NULL, "illegal address for code patching");
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NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
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if (os::is_MP()) {
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guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
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}
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// First patch dummy jmp in place
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unsigned char patch[4];
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assert(sizeof(patch)==sizeof(jint), "sanity check");
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patch[0] = 0xEB; // jmp rel8
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patch[1] = 0xFE; // jmp to self
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patch[2] = 0xEB;
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patch[3] = 0xFE;
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// First patch dummy jmp in place
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*(jint*)instr_addr = *(jint *)patch;
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// Invalidate. Opteron requires a flush after every write.
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n_call->wrote(0);
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// Patch 4th byte
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instr_addr[4] = code_buffer[4];
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n_call->wrote(4);
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// Patch bytes 0-3
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*(jint*)instr_addr = *(jint *)code_buffer;
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n_call->wrote(0);
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#ifdef ASSERT
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// verify patching
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for ( int i = 0; i < instruction_size; i++) {
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address ptr = (address)((intptr_t)code_buffer + i);
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int a_byte = (*ptr) & 0xFF;
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assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
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}
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#endif
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}
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// Similar to replace_mt_safe, but just changes the destination. The
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// important thing is that free-running threads are able to execute this
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// call instruction at all times. If the displacement field is aligned
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// we can simply rely on atomicity of 32-bit writes to make sure other threads
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// will see no intermediate states. Otherwise, the first two bytes of the
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// call are guaranteed to be aligned, and can be atomically patched to a
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// self-loop to guard the instruction while we change the other bytes.
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// We cannot rely on locks here, since the free-running threads must run at
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// full speed.
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//
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// Used in the runtime linkage of calls; see class CompiledIC.
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// (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
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void NativeCall::set_destination_mt_safe(address dest) {
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debug_only(verify());
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// Make sure patching code is locked. No two threads can patch at the same
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// time but one may be executing this code.
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assert(Patching_lock->is_locked() ||
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SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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// Both C1 and C2 should now be generating code which aligns the patched address
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// to be within a single cache line except that C1 does not do the alignment on
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// uniprocessor systems.
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bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
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((uintptr_t)displacement_address() + 3) / cache_line_size;
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guarantee(!os::is_MP() || is_aligned, "destination must be aligned");
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if (is_aligned) {
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// Simple case: The destination lies within a single cache line.
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set_destination(dest);
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} else if ((uintptr_t)instruction_address() / cache_line_size ==
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((uintptr_t)instruction_address()+1) / cache_line_size) {
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// Tricky case: The instruction prefix lies within a single cache line.
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intptr_t disp = dest - return_address();
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#ifdef AMD64
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guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
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#endif // AMD64
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int call_opcode = instruction_address()[0];
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// First patch dummy jump in place:
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{
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u_char patch_jump[2];
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patch_jump[0] = 0xEB; // jmp rel8
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patch_jump[1] = 0xFE; // jmp to self
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assert(sizeof(patch_jump)==sizeof(short), "sanity check");
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*(short*)instruction_address() = *(short*)patch_jump;
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}
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// Invalidate. Opteron requires a flush after every write.
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wrote(0);
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// (Note: We assume any reader which has already started to read
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// the unpatched call will completely read the whole unpatched call
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// without seeing the next writes we are about to make.)
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// Next, patch the last three bytes:
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u_char patch_disp[5];
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patch_disp[0] = call_opcode;
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*(int32_t*)&patch_disp[1] = (int32_t)disp;
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assert(sizeof(patch_disp)==instruction_size, "sanity check");
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for (int i = sizeof(short); i < instruction_size; i++)
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instruction_address()[i] = patch_disp[i];
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// Invalidate. Opteron requires a flush after every write.
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wrote(sizeof(short));
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// (Note: We assume that any reader which reads the opcode we are
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// about to repatch will also read the writes we just made.)
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// Finally, overwrite the jump:
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*(short*)instruction_address() = *(short*)patch_disp;
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// Invalidate. Opteron requires a flush after every write.
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wrote(0);
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debug_only(verify());
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guarantee(destination() == dest, "patch succeeded");
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} else {
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// Impossible: One or the other must be atomically writable.
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ShouldNotReachHere();
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}
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}
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void NativeMovConstReg::verify() {
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#ifdef AMD64
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// make sure code pattern is actually a mov reg64, imm64 instruction
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if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
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(ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
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print();
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fatal("not a REX.W[B] mov reg64, imm64");
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}
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#else
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// make sure code pattern is actually a mov reg, imm32 instruction
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u_char test_byte = *(u_char*)instruction_address();
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u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
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if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
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#endif // AMD64
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}
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void NativeMovConstReg::print() {
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tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
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instruction_address(), data());
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}
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//-------------------------------------------------------------------
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int NativeMovRegMem::instruction_start() const {
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int off = 0;
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u_char instr_0 = ubyte_at(off);
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// See comment in Assembler::locate_operand() about VEX prefixes.
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if (instr_0 == instruction_VEX_prefix_2bytes) {
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assert((UseAVX > 0), "shouldn't have VEX prefix");
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NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
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return 2;
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}
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if (instr_0 == instruction_VEX_prefix_3bytes) {
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assert((UseAVX > 0), "shouldn't have VEX prefix");
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NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
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return 3;
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}
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// First check to see if we have a (prefixed or not) xor
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if (instr_0 >= instruction_prefix_wide_lo && // 0x40
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instr_0 <= instruction_prefix_wide_hi) { // 0x4f
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off++;
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instr_0 = ubyte_at(off);
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}
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if (instr_0 == instruction_code_xor) {
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off += 2;
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instr_0 = ubyte_at(off);
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}
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// Now look for the real instruction and the many prefix/size specifiers.
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if (instr_0 == instruction_operandsize_prefix ) { // 0x66
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off++; // Not SSE instructions
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instr_0 = ubyte_at(off);
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}
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if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3
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instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
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off++;
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instr_0 = ubyte_at(off);
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}
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if ( instr_0 >= instruction_prefix_wide_lo && // 0x40
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instr_0 <= instruction_prefix_wide_hi) { // 0x4f
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off++;
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instr_0 = ubyte_at(off);
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}
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if (instr_0 == instruction_extended_prefix ) { // 0x0f
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off++;
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}
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return off;
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}
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address NativeMovRegMem::instruction_address() const {
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return addr_at(instruction_start());
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}
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address NativeMovRegMem::next_instruction_address() const {
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address ret = instruction_address() + instruction_size;
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u_char instr_0 = *(u_char*) instruction_address();
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switch (instr_0) {
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case instruction_operandsize_prefix:
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fatal("should have skipped instruction_operandsize_prefix");
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break;
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case instruction_extended_prefix:
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fatal("should have skipped instruction_extended_prefix");
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break;
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case instruction_code_mem2reg_movslq: // 0x63
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case instruction_code_mem2reg_movzxb: // 0xB6
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case instruction_code_mem2reg_movsxb: // 0xBE
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case instruction_code_mem2reg_movzxw: // 0xB7
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case instruction_code_mem2reg_movsxw: // 0xBF
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case instruction_code_reg2mem: // 0x89 (q/l)
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case instruction_code_mem2reg: // 0x8B (q/l)
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case instruction_code_reg2memb: // 0x88
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case instruction_code_mem2regb: // 0x8a
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case instruction_code_float_s: // 0xd9 fld_s a
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case instruction_code_float_d: // 0xdd fld_d a
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case instruction_code_xmm_load: // 0x10
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case instruction_code_xmm_store: // 0x11
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case instruction_code_xmm_lpd: // 0x12
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{
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// If there is an SIB then instruction is longer than expected
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u_char mod_rm = *(u_char*)(instruction_address() + 1);
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if ((mod_rm & 7) == 0x4) {
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ret++;
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}
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}
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case instruction_code_xor:
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fatal("should have skipped xor lead in");
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break;
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default:
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fatal("not a NativeMovRegMem");
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}
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return ret;
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}
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int NativeMovRegMem::offset() const{
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int off = data_offset + instruction_start();
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u_char mod_rm = *(u_char*)(instruction_address() + 1);
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// nnnn(r12|rsp) isn't coded as simple mod/rm since that is
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// the encoding to use an SIB byte. Which will have the nnnn
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// field off by one byte
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if ((mod_rm & 7) == 0x4) {
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off++;
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}
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return int_at(off);
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}
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void NativeMovRegMem::set_offset(int x) {
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int off = data_offset + instruction_start();
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u_char mod_rm = *(u_char*)(instruction_address() + 1);
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// nnnn(r12|rsp) isn't coded as simple mod/rm since that is
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// the encoding to use an SIB byte. Which will have the nnnn
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// field off by one byte
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if ((mod_rm & 7) == 0x4) {
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off++;
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}
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set_int_at(off, x);
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}
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void NativeMovRegMem::verify() {
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// make sure code pattern is actually a mov [reg+offset], reg instruction
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u_char test_byte = *(u_char*)instruction_address();
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switch (test_byte) {
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case instruction_code_reg2memb: // 0x88 movb a, r
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case instruction_code_reg2mem: // 0x89 movl a, r (can be movq in 64bit)
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case instruction_code_mem2regb: // 0x8a movb r, a
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case instruction_code_mem2reg: // 0x8b movl r, a (can be movq in 64bit)
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break;
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case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
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case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
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case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
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case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
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case instruction_code_mem2reg_movsxw: // 0xbf movswl r, a (movsxw)
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break;
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case instruction_code_float_s: // 0xd9 fld_s a
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case instruction_code_float_d: // 0xdd fld_d a
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case instruction_code_xmm_load: // 0x10 movsd xmm, a
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case instruction_code_xmm_store: // 0x11 movsd a, xmm
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case instruction_code_xmm_lpd: // 0x12 movlpd xmm, a
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break;
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default:
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fatal ("not a mov [reg+offs], reg instruction");
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}
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}
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void NativeMovRegMem::print() {
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tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
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}
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//-------------------------------------------------------------------
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void NativeLoadAddress::verify() {
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// make sure code pattern is actually a mov [reg+offset], reg instruction
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u_char test_byte = *(u_char*)instruction_address();
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#ifdef _LP64
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if ( (test_byte == instruction_prefix_wide ||
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test_byte == instruction_prefix_wide_extended) ) {
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test_byte = *(u_char*)(instruction_address() + 1);
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}
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#endif // _LP64
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if ( ! ((test_byte == lea_instruction_code)
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LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) {
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fatal ("not a lea reg, [reg+offs] instruction");
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}
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}
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void NativeLoadAddress::print() {
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tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
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}
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//--------------------------------------------------------------------------------
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void NativeJump::verify() {
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if (*(u_char*)instruction_address() != instruction_code) {
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fatal("not a jump instruction");
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}
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}
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void NativeJump::insert(address code_pos, address entry) {
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intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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#ifdef AMD64
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guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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#endif // AMD64
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*code_pos = instruction_code;
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*((int32_t*)(code_pos + 1)) = (int32_t)disp;
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ICache::invalidate_range(code_pos, instruction_size);
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}
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void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
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// Patching to not_entrant can happen while activations of the method are
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// in use. The patching in that instance must happen only when certain
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// alignment restrictions are true. These guarantees check those
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// conditions.
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#ifdef AMD64
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const int linesize = 64;
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#else
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const int linesize = 32;
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#endif // AMD64
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// Must be wordSize aligned
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guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
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"illegal address for code patching 2");
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// First 5 bytes must be within the same cache line - 4827828
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guarantee((uintptr_t) verified_entry / linesize ==
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((uintptr_t) verified_entry + 4) / linesize,
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"illegal address for code patching 3");
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}
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// MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
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// The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
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// First patches the first word atomically to be a jump to itself.
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// Then patches the last byte and then atomically patches the first word (4-bytes),
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// thus inserting the desired jump
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// This code is mt-safe with the following conditions: entry point is 4 byte aligned,
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// entry point is in same cache line as unverified entry point, and the instruction being
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// patched is >= 5 byte (size of patch).
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//
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// In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
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// In C1 the restriction is enforced by CodeEmitter::method_entry
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//
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void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
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// complete jump instruction (to be inserted) is in code_buffer;
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unsigned char code_buffer[5];
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code_buffer[0] = instruction_code;
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intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
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#ifdef AMD64
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guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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#endif // AMD64
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*(int32_t*)(code_buffer + 1) = (int32_t)disp;
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check_verified_entry_alignment(entry, verified_entry);
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// Can't call nativeJump_at() because it's asserts jump exists
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NativeJump* n_jump = (NativeJump*) verified_entry;
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//First patch dummy jmp in place
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unsigned char patch[4];
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assert(sizeof(patch)==sizeof(int32_t), "sanity check");
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patch[0] = 0xEB; // jmp rel8
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patch[1] = 0xFE; // jmp to self
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patch[2] = 0xEB;
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patch[3] = 0xFE;
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// First patch dummy jmp in place
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*(int32_t*)verified_entry = *(int32_t *)patch;
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n_jump->wrote(0);
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// Patch 5th byte (from jump instruction)
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verified_entry[4] = code_buffer[4];
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n_jump->wrote(4);
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// Patch bytes 0-3 (from jump instruction)
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*(int32_t*)verified_entry = *(int32_t *)code_buffer;
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// Invalidate. Opteron requires a flush after every write.
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n_jump->wrote(0);
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}
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void NativePopReg::insert(address code_pos, Register reg) {
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assert(reg->encoding() < 8, "no space for REX");
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assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
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*code_pos = (u_char)(instruction_code | reg->encoding());
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ICache::invalidate_range(code_pos, instruction_size);
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}
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void NativeIllegalInstruction::insert(address code_pos) {
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assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
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*(short *)code_pos = instruction_code;
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ICache::invalidate_range(code_pos, instruction_size);
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}
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void NativeGeneralJump::verify() {
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assert(((NativeInstruction *)this)->is_jump() ||
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((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
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}
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void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
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intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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#ifdef AMD64
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guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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#endif // AMD64
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*code_pos = unconditional_long_jump;
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*((int32_t *)(code_pos+1)) = (int32_t) disp;
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ICache::invalidate_range(code_pos, instruction_size);
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}
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// MT-safe patching of a long jump instruction.
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// First patches first word of instruction to two jmp's that jmps to them
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// selfs (spinlock). Then patches the last byte, and then atomicly replaces
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// the jmp's with the first 4 byte of the new instruction.
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void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
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assert (instr_addr != NULL, "illegal address for code patching (4)");
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NativeGeneralJump* n_jump = nativeGeneralJump_at (instr_addr); // checking that it is a jump
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// Temporary code
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unsigned char patch[4];
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assert(sizeof(patch)==sizeof(int32_t), "sanity check");
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patch[0] = 0xEB; // jmp rel8
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patch[1] = 0xFE; // jmp to self
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patch[2] = 0xEB;
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patch[3] = 0xFE;
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// First patch dummy jmp in place
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*(int32_t*)instr_addr = *(int32_t *)patch;
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n_jump->wrote(0);
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// Patch 4th byte
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instr_addr[4] = code_buffer[4];
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n_jump->wrote(4);
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// Patch bytes 0-3
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*(jint*)instr_addr = *(jint *)code_buffer;
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n_jump->wrote(0);
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#ifdef ASSERT
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// verify patching
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for ( int i = 0; i < instruction_size; i++) {
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address ptr = (address)((intptr_t)code_buffer + i);
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int a_byte = (*ptr) & 0xFF;
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assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
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}
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#endif
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}
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address NativeGeneralJump::jump_destination() const {
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int op_code = ubyte_at(0);
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bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
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int offset = (op_code == 0x0F) ? 2 : 1;
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int length = offset + ((is_rel32off) ? 4 : 1);
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if (is_rel32off)
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return addr_at(0) + length + int_at(offset);
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else
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return addr_at(0) + length + sbyte_at(offset);
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}
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