432 lines
15 KiB
C++
432 lines
15 KiB
C++
/*
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* Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_ARM_VM_NATIVEINST_ARM_32_HPP
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#define CPU_ARM_VM_NATIVEINST_ARM_32_HPP
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#include "asm/macroAssembler.hpp"
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#include "code/codeCache.hpp"
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#include "runtime/icache.hpp"
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#include "runtime/os.hpp"
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#include "runtime/thread.hpp"
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#include "register_arm.hpp"
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// -------------------------------------------------------------------
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// Some experimental projects extend the ARM back-end by implementing
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// what the front-end usually assumes is a single native instruction
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// with a sequence of instructions.
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//
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// The 'Raw' variants are the low level initial code (usually one
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// instruction wide but some of them were already composed
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// instructions). They should be used only by the back-end.
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//
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// The non-raw classes are the front-end entry point, hiding potential
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// back-end extensions or the actual instructions size.
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class NativeInstruction;
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class RawNativeInstruction {
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public:
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enum ARM_specific {
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instruction_size = Assembler::InstructionSize
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};
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enum InstructionKind {
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instr_ldr_str = 0x50,
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instr_ldrh_strh = 0x10,
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instr_fld_fst = 0xd0
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};
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// illegal instruction used by NativeJump::patch_verified_entry
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// permanently undefined (UDF): 0xe << 28 | 0b1111111 << 20 | 0b1111 << 4
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static const int zombie_illegal_instruction = 0xe7f000f0;
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static int decode_rotated_imm12(int encoding) {
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int base = encoding & 0xff;
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int right_rotation = (encoding & 0xf00) >> 7;
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int left_rotation = 32 - right_rotation;
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int val = (base >> right_rotation) | (base << left_rotation);
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return val;
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}
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address addr_at(int offset) const { return (address)this + offset; }
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address instruction_address() const { return addr_at(0); }
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address next_raw_instruction_address() const { return addr_at(instruction_size); }
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static RawNativeInstruction* at(address address) {
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return (RawNativeInstruction*)address;
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}
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RawNativeInstruction* next_raw() const {
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return at(next_raw_instruction_address());
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}
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public:
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int encoding() const { return *(int*)this; }
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void set_encoding(int value) {
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int old = *(int*)this;
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if (old != value) {
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*(int*)this = value;
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ICache::invalidate_word((address)this);
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}
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}
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InstructionKind kind() const {
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return (InstructionKind) ((encoding() >> 20) & 0xf2);
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}
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bool is_nop() const { return encoding() == (int)0xe1a00000; }
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bool is_b() const { return (encoding() & 0x0f000000) == 0x0a000000; }
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bool is_bx() const { return (encoding() & 0x0ffffff0) == 0x012fff10; }
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bool is_bl() const { return (encoding() & 0x0f000000) == 0x0b000000; }
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bool is_blx() const { return (encoding() & 0x0ffffff0) == 0x012fff30; }
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bool is_fat_call() const {
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return (is_add_lr() && next_raw()->is_jump());
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}
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bool is_ldr_call() const {
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return (is_add_lr() && next_raw()->is_ldr_pc());
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}
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bool is_jump() const { return is_b() || is_ldr_pc(); }
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bool is_call() const { return is_bl() || is_fat_call(); }
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bool is_branch() const { return is_b() || is_bl(); }
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bool is_far_branch() const { return is_movw() || is_ldr_literal(); }
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bool is_ldr_literal() const {
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// ldr Rx, [PC, #offset] for positive or negative offsets
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return (encoding() & 0x0f7f0000) == 0x051f0000;
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}
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bool is_ldr() const {
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// ldr Rd, [Rn, #offset] for positive or negative offsets
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return (encoding() & 0x0f700000) == 0x05100000;
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}
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int ldr_offset() const {
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assert(is_ldr(), "must be");
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int offset = encoding() & 0xfff;
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if (encoding() & (1 << 23)) {
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// positive offset
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} else {
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// negative offset
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offset = -offset;
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}
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return offset;
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}
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// is_ldr_pc: ldr PC, PC, #offset
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bool is_ldr_pc() const { return (encoding() & 0x0f7ff000) == 0x051ff000; }
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// is_setting_pc(): ldr PC, Rxx, #offset
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bool is_setting_pc() const { return (encoding() & 0x0f70f000) == 0x0510f000; }
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bool is_add_lr() const { return (encoding() & 0x0ffff000) == 0x028fe000; }
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bool is_add_pc() const { return (encoding() & 0x0fff0000) == 0x028f0000; }
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bool is_sub_pc() const { return (encoding() & 0x0fff0000) == 0x024f0000; }
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bool is_pc_rel() const { return is_add_pc() || is_sub_pc(); }
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bool is_movw() const { return (encoding() & 0x0ff00000) == 0x03000000; }
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bool is_movt() const { return (encoding() & 0x0ff00000) == 0x03400000; }
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// c2 doesn't use fixed registers for safepoint poll address
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bool is_safepoint_poll() const { return (encoding() & 0xfff0ffff) == 0xe590c000; }
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// For unit tests
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static void test() {}
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};
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inline RawNativeInstruction* rawNativeInstruction_at(address address) {
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return (RawNativeInstruction*)address;
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}
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// Base class exported to the front-end
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class NativeInstruction: public RawNativeInstruction {
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public:
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static NativeInstruction* at(address address) {
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return (NativeInstruction*)address;
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}
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public:
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// No need to consider indirections while parsing NativeInstruction
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address next_instruction_address() const {
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return next_raw_instruction_address();
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}
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// next() is no longer defined to avoid confusion.
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//
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// The front end and most classes except for those defined in nativeInst_arm
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// or relocInfo_arm should only use next_instruction_address(), skipping
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// over composed instruction and ignoring back-end extensions.
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//
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// The back-end can use next_raw() when it knows the instruction sequence
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// and only wants to skip a single native instruction.
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};
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inline NativeInstruction* nativeInstruction_at(address address) {
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return (NativeInstruction*)address;
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}
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// -------------------------------------------------------------------
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// Raw b() or bl() instructions, not used by the front-end.
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class RawNativeBranch: public RawNativeInstruction {
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public:
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address destination(int adj = 0) const {
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return instruction_address() + (encoding() << 8 >> 6) + 8 + adj;
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}
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void set_destination(address dest) {
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int new_offset = (int)(dest - instruction_address() - 8);
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assert(new_offset < 0x2000000 && new_offset > -0x2000000, "encoding constraint");
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set_encoding((encoding() & 0xff000000) | ((unsigned int)new_offset << 6 >> 8));
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}
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};
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inline RawNativeBranch* rawNativeBranch_at(address address) {
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assert(rawNativeInstruction_at(address)->is_branch(), "must be");
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return (RawNativeBranch*)address;
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}
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class NativeBranch: public RawNativeBranch {
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};
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inline NativeBranch* nativeBranch_at(address address) {
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return (NativeBranch *) rawNativeBranch_at(address);
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}
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// -------------------------------------------------------------------
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// NativeGeneralJump is for patchable internal (near) jumps
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// It is used directly by the front-end and must be a single instruction wide
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// (to support patching to other kind of instructions).
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class NativeGeneralJump: public RawNativeInstruction {
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public:
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address jump_destination() const {
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return rawNativeBranch_at(instruction_address())->destination();
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}
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void set_jump_destination(address dest) {
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return rawNativeBranch_at(instruction_address())->set_destination(dest);
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}
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static void insert_unconditional(address code_pos, address entry);
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static void replace_mt_safe(address instr_addr, address code_buffer) {
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assert(((int)instr_addr & 3) == 0 && ((int)code_buffer & 3) == 0, "must be aligned");
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// Writing a word is atomic on ARM, so no MT-safe tricks are needed
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rawNativeInstruction_at(instr_addr)->set_encoding(*(int*)code_buffer);
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}
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};
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inline NativeGeneralJump* nativeGeneralJump_at(address address) {
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assert(rawNativeInstruction_at(address)->is_jump(), "must be");
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return (NativeGeneralJump*)address;
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}
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// -------------------------------------------------------------------
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class RawNativeJump: public NativeInstruction {
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public:
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address jump_destination(int adj = 0) const {
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address a;
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if (is_b()) {
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a = rawNativeBranch_at(instruction_address())->destination(adj);
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// Jump destination -1 is encoded as a jump to self
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if (a == instruction_address()) {
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return (address)-1;
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}
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} else {
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assert(is_ldr_pc(), "must be");
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int offset = this->ldr_offset();
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a = *(address*)(instruction_address() + 8 + offset);
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}
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return a;
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}
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void set_jump_destination(address dest) {
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address a;
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if (is_b()) {
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// Jump destination -1 is encoded as a jump to self
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if (dest == (address)-1) {
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dest = instruction_address();
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}
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rawNativeBranch_at(instruction_address())->set_destination(dest);
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} else {
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assert(is_ldr_pc(), "must be");
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int offset = this->ldr_offset();
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*(address*)(instruction_address() + 8 + offset) = dest;
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OrderAccess::storeload(); // overkill if caller holds lock?
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}
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}
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static void check_verified_entry_alignment(address entry, address verified_entry);
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static void patch_verified_entry(address entry, address verified_entry, address dest);
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};
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inline RawNativeJump* rawNativeJump_at(address address) {
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assert(rawNativeInstruction_at(address)->is_jump(), "must be");
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return (RawNativeJump*)address;
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}
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// -------------------------------------------------------------------
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class RawNativeCall: public NativeInstruction {
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// See IC calls in LIR_Assembler::ic_call(): ARM v5/v6 doesn't use a
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// single bl for IC calls.
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public:
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address return_address() const {
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if (is_bl()) {
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return addr_at(instruction_size);
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} else {
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assert(is_fat_call(), "must be");
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int offset = encoding() & 0xff;
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return addr_at(offset + 8);
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}
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}
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address destination(int adj = 0) const {
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if (is_bl()) {
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return rawNativeBranch_at(instruction_address())->destination(adj);
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} else {
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assert(is_add_lr(), "must be"); // fat_call
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RawNativeJump *next = rawNativeJump_at(next_raw_instruction_address());
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return next->jump_destination(adj);
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}
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}
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void set_destination(address dest) {
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if (is_bl()) {
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return rawNativeBranch_at(instruction_address())->set_destination(dest);
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} else {
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assert(is_add_lr(), "must be"); // fat_call
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RawNativeJump *next = rawNativeJump_at(next_raw_instruction_address());
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return next->set_jump_destination(dest);
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}
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}
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void set_destination_mt_safe(address dest) {
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assert(CodeCache::contains(dest), "external destination might be too far");
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set_destination(dest);
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}
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void verify() {
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assert(RawNativeInstruction::is_call() || (!VM_Version::supports_movw() && RawNativeInstruction::is_jump()), "must be");
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}
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void verify_alignment() {
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// Nothing to do on ARM
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}
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static bool is_call_before(address return_address);
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};
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inline RawNativeCall* rawNativeCall_at(address address) {
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assert(rawNativeInstruction_at(address)->is_call(), "must be");
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return (RawNativeCall*)address;
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}
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NativeCall* rawNativeCall_before(address return_address);
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// -------------------------------------------------------------------
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// NativeMovRegMem need not be extended with indirection support.
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// (field access patching is handled differently in that case)
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class NativeMovRegMem: public NativeInstruction {
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public:
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int offset() const;
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void set_offset(int x);
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void add_offset_in_bytes(int add_offset) {
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set_offset(offset() + add_offset);
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}
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};
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inline NativeMovRegMem* nativeMovRegMem_at(address address) {
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NativeMovRegMem* instr = (NativeMovRegMem*)address;
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assert(instr->kind() == NativeInstruction::instr_ldr_str ||
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instr->kind() == NativeInstruction::instr_ldrh_strh ||
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instr->kind() == NativeInstruction::instr_fld_fst, "must be");
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return instr;
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}
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// -------------------------------------------------------------------
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// NativeMovConstReg is primarily for loading oops and metadata
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class NativeMovConstReg: public NativeInstruction {
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public:
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intptr_t data() const;
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void set_data(intptr_t x, address pc = 0);
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bool is_pc_relative() {
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return !is_movw();
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}
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void set_pc_relative_offset(address addr, address pc);
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address next_instruction_address() const {
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// NOTE: CompiledStaticCall::set_to_interpreted() calls this but
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// are restricted to single-instruction ldr. No need to jump over
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// several instructions.
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assert(is_ldr_literal(), "Should only use single-instructions load");
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return next_raw_instruction_address();
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}
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};
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inline NativeMovConstReg* nativeMovConstReg_at(address address) {
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NativeInstruction* ni = nativeInstruction_at(address);
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assert(ni->is_ldr_literal() || ni->is_pc_rel() ||
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ni->is_movw() && VM_Version::supports_movw(), "must be");
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return (NativeMovConstReg*)address;
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}
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// -------------------------------------------------------------------
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// Front end classes, hiding experimental back-end extensions.
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// Extension to support indirections
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class NativeJump: public RawNativeJump {
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public:
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};
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inline NativeJump* nativeJump_at(address address) {
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assert(nativeInstruction_at(address)->is_jump(), "must be");
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return (NativeJump*)address;
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}
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class NativeCall: public RawNativeCall {
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public:
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// NativeCall::next_instruction_address() is used only to define the
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// range where to look for the relocation information. We need not
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// walk over composed instructions (as long as the relocation information
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// is associated to the first instruction).
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address next_instruction_address() const {
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return next_raw_instruction_address();
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}
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};
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inline NativeCall* nativeCall_at(address address) {
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assert(nativeInstruction_at(address)->is_call() ||
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(!VM_Version::supports_movw() && nativeInstruction_at(address)->is_jump()), "must be");
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return (NativeCall*)address;
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}
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inline NativeCall* nativeCall_before(address return_address) {
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return (NativeCall *) rawNativeCall_before(return_address);
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}
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#endif // CPU_ARM_VM_NATIVEINST_ARM_32_HPP
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