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8299847: RISC-V: Improve PrintOptoAssembly output of CMoveI/L nodes

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Reviewed-by: fjiang, shade
This commit is contained in:
Fei Yang 2023-01-17 03:06:57 +00:00
parent 240830df7e
commit 859ccd1a15
1 changed files with 29 additions and 40 deletions
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69
src/hotspot/cpu/riscv/riscv.ad
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@ -940,7 +940,7 @@ definitions %{
int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
int_def BRANCH_COST ( 100, 1 * DEFAULT_COST); // branch, jmp, call
int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi
int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi
@ -3817,13 +3817,13 @@ operand cmpOpULtGe()
format %{ "" %}
interface(COND_INTER) %{
equal(0x0, "eq");
greater(0x1, "gt");
greater(0x1, "gtu");
overflow(0x2, "overflow");
less(0x3, "lt");
less(0x3, "ltu");
not_equal(0x4, "ne");
less_equal(0x5, "le");
less_equal(0x5, "leu");
no_overflow(0x6, "no_overflow");
greater_equal(0x7, "ge");
greater_equal(0x7, "geu");
%}
%}
@ -3839,13 +3839,13 @@ operand cmpOpUEqNeLeGt()
format %{ "" %}
interface(COND_INTER) %{
equal(0x0, "eq");
greater(0x1, "gt");
greater(0x1, "gtu");
overflow(0x2, "overflow");
less(0x3, "lt");
less(0x3, "ltu");
not_equal(0x4, "ne");
less_equal(0x5, "le");
less_equal(0x5, "leu");
no_overflow(0x6, "no_overflow");
greater_equal(0x7, "ge");
greater_equal(0x7, "geu");
%}
%}
@ -4373,7 +4373,7 @@ pipe_class istore_reg_reg(iRegI dst, iRegI src)
LDST : MEM;
%}
//------- Store pipeline operations -----------------------
//------- Control transfer pipeline operations ------------
// Branch
pipe_class pipe_branch()
@ -9890,10 +9890,8 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode,
@ -9901,7 +9899,7 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}
instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
@ -9909,10 +9907,8 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop)
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
@ -9920,7 +9916,7 @@ instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop)
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}
instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
@ -9928,10 +9924,8 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode,
@ -9939,7 +9933,7 @@ instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}
instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
@ -9947,10 +9941,8 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode,
@ -9958,7 +9950,7 @@ instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}
instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
@ -9966,10 +9958,8 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop)
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
@ -9977,17 +9967,16 @@ instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop)
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}
instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);
format %{
"bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
%}
ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
@ -9995,7 +9984,7 @@ instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop)
as_Register($dst$$reg), as_Register($src$$reg));
%}
ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}