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8247695: PPC/S390: compiler/intrinsics/math/TestFpMinMaxIntrinsics.java fails

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Reviewed-by: goetz, lucy
This commit is contained in:
Richard Reingruber 2020-07-13 10:33:14 +02:00
parent 2d3c928f0b
commit 870e67d520
2 changed files with 25 additions and 1 deletions
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13
src/hotspot/cpu/ppc/ppc.ad
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@ -9203,6 +9203,19 @@ instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
ins_pipe(pipe_class_default); ins_pipe(pipe_class_default);
%} %}
instruct absL_reg_Ex(iRegLdst dst, iRegLsrc src) %{
match(Set dst (AbsL src));
ins_cost(DEFAULT_COST*3);
expand %{
iRegLdst tmp1;
iRegLdst tmp2;
signmask64L_regL(tmp1, src);
xorL_reg_reg(tmp2, tmp1, src);
subL_reg_reg(dst, tmp2, tmp1);
%}
%}
// Long negation // Long negation
instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
match(Set dst (SubL zero src2)); match(Set dst (SubL zero src2));

13
src/hotspot/cpu/s390/s390.ad
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@ -1,6 +1,6 @@
// //
// Copyright (c) 2017, 2020, Oracle and/or its affiliates. All rights reserved. // Copyright (c) 2017, 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2017, 2019 SAP SE. All rights reserved. // Copyright (c) 2017, 2020 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// //
// This code is free software; you can redistribute it and/or modify it // This code is free software; you can redistribute it and/or modify it
@ -9050,6 +9050,17 @@ instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
ins_pipe(pipe_class_dummy); ins_pipe(pipe_class_dummy);
%} %}
instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
match(Set dst (AbsL src));
effect(KILL cr);
ins_cost(DEFAULT_COST_LOW);
// TODO: s390 port size(FIXED_SIZE);
format %{ "LPGR $dst, $src" %}
opcode(LPGR_ZOPC);
ins_encode(z_rreform(dst, src));
ins_pipe(pipe_class_dummy);
%}
instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{ instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
match(Set dst (SubI zero (AbsI src))); match(Set dst (SubI zero (AbsI src)));
effect(KILL cr); effect(KILL cr);