294 lines
10 KiB
C++
294 lines
10 KiB
C++
/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "c1/c1_FrameMap.hpp"
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#include "c1/c1_LIR.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "vmreg_s390.inline.hpp"
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const int FrameMap::pd_c_runtime_reserved_arg_size = 7;
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LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) {
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LIR_Opr opr = LIR_OprFact::illegalOpr;
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VMReg r_1 = reg->first();
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VMReg r_2 = reg->second();
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if (r_1->is_stack()) {
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// Convert stack slot to an SP offset.
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// The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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// so we must add it in here.
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int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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opr = LIR_OprFact::address(new LIR_Address(Z_SP_opr, st_off, type));
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} else if (r_1->is_Register()) {
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Register reg = r_1->as_Register();
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if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
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opr = as_long_opr(reg);
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} else if (type == T_OBJECT || type == T_ARRAY) {
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opr = as_oop_opr(reg);
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} else if (type == T_METADATA) {
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opr = as_metadata_opr(reg);
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} else {
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opr = as_opr(reg);
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}
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} else if (r_1->is_FloatRegister()) {
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assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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FloatRegister f = r_1->as_FloatRegister();
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if (type == T_FLOAT) {
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opr = as_float_opr(f);
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} else {
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opr = as_double_opr(f);
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}
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} else {
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ShouldNotReachHere();
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}
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return opr;
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}
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// FrameMap
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//--------------------------------------------------------
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FloatRegister FrameMap::_fpu_rnr2reg [FrameMap::nof_fpu_regs]; // mapping c1 regnr. -> FloatRegister
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int FrameMap::_fpu_reg2rnr [FrameMap::nof_fpu_regs]; // mapping assembler encoding -> c1 regnr.
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// Some useful constant RInfo's:
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LIR_Opr FrameMap::Z_R0_opr;
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LIR_Opr FrameMap::Z_R1_opr;
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LIR_Opr FrameMap::Z_R2_opr;
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LIR_Opr FrameMap::Z_R3_opr;
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LIR_Opr FrameMap::Z_R4_opr;
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LIR_Opr FrameMap::Z_R5_opr;
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LIR_Opr FrameMap::Z_R6_opr;
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LIR_Opr FrameMap::Z_R7_opr;
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LIR_Opr FrameMap::Z_R8_opr;
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LIR_Opr FrameMap::Z_R9_opr;
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LIR_Opr FrameMap::Z_R10_opr;
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LIR_Opr FrameMap::Z_R11_opr;
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LIR_Opr FrameMap::Z_R12_opr;
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LIR_Opr FrameMap::Z_R13_opr;
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LIR_Opr FrameMap::Z_R14_opr;
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LIR_Opr FrameMap::Z_R15_opr;
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LIR_Opr FrameMap::Z_R0_oop_opr;
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LIR_Opr FrameMap::Z_R1_oop_opr;
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LIR_Opr FrameMap::Z_R2_oop_opr;
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LIR_Opr FrameMap::Z_R3_oop_opr;
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LIR_Opr FrameMap::Z_R4_oop_opr;
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LIR_Opr FrameMap::Z_R5_oop_opr;
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LIR_Opr FrameMap::Z_R6_oop_opr;
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LIR_Opr FrameMap::Z_R7_oop_opr;
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LIR_Opr FrameMap::Z_R8_oop_opr;
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LIR_Opr FrameMap::Z_R9_oop_opr;
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LIR_Opr FrameMap::Z_R10_oop_opr;
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LIR_Opr FrameMap::Z_R11_oop_opr;
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LIR_Opr FrameMap::Z_R12_oop_opr;
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LIR_Opr FrameMap::Z_R13_oop_opr;
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LIR_Opr FrameMap::Z_R14_oop_opr;
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LIR_Opr FrameMap::Z_R15_oop_opr;
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LIR_Opr FrameMap::Z_R0_metadata_opr;
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LIR_Opr FrameMap::Z_R1_metadata_opr;
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LIR_Opr FrameMap::Z_R2_metadata_opr;
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LIR_Opr FrameMap::Z_R3_metadata_opr;
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LIR_Opr FrameMap::Z_R4_metadata_opr;
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LIR_Opr FrameMap::Z_R5_metadata_opr;
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LIR_Opr FrameMap::Z_R6_metadata_opr;
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LIR_Opr FrameMap::Z_R7_metadata_opr;
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LIR_Opr FrameMap::Z_R8_metadata_opr;
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LIR_Opr FrameMap::Z_R9_metadata_opr;
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LIR_Opr FrameMap::Z_R10_metadata_opr;
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LIR_Opr FrameMap::Z_R11_metadata_opr;
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LIR_Opr FrameMap::Z_R12_metadata_opr;
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LIR_Opr FrameMap::Z_R13_metadata_opr;
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LIR_Opr FrameMap::Z_R14_metadata_opr;
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LIR_Opr FrameMap::Z_R15_metadata_opr;
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LIR_Opr FrameMap::Z_SP_opr;
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LIR_Opr FrameMap::Z_FP_opr;
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LIR_Opr FrameMap::Z_R2_long_opr;
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LIR_Opr FrameMap::Z_R10_long_opr;
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LIR_Opr FrameMap::Z_R11_long_opr;
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LIR_Opr FrameMap::Z_F0_opr;
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LIR_Opr FrameMap::Z_F0_double_opr;
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LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
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LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
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// c1 rnr -> FloatRegister
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FloatRegister FrameMap::nr2floatreg (int rnr) {
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assert(_init_done, "tables not initialized");
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debug_only(fpu_range_check(rnr);)
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return _fpu_rnr2reg[rnr];
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}
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void FrameMap::map_float_register(int rnr, FloatRegister reg) {
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debug_only(fpu_range_check(rnr);)
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debug_only(fpu_range_check(reg->encoding());)
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_fpu_rnr2reg[rnr] = reg; // mapping c1 regnr. -> FloatRegister
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_fpu_reg2rnr[reg->encoding()] = rnr; // mapping assembler encoding -> c1 regnr.
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}
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void FrameMap::initialize() {
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assert(!_init_done, "once");
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DEBUG_ONLY(int allocated = 0;)
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DEBUG_ONLY(int unallocated = 0;)
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// Register usage:
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// Z_thread (Z_R8)
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// Z_fp (Z_R9)
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// Z_SP (Z_R15)
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DEBUG_ONLY(allocated++); map_register(0, Z_R2);
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DEBUG_ONLY(allocated++); map_register(1, Z_R3);
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DEBUG_ONLY(allocated++); map_register(2, Z_R4);
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DEBUG_ONLY(allocated++); map_register(3, Z_R5);
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DEBUG_ONLY(allocated++); map_register(4, Z_R6);
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DEBUG_ONLY(allocated++); map_register(5, Z_R7);
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DEBUG_ONLY(allocated++); map_register(6, Z_R10);
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DEBUG_ONLY(allocated++); map_register(7, Z_R11);
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DEBUG_ONLY(allocated++); map_register(8, Z_R12);
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DEBUG_ONLY(allocated++); map_register(9, Z_R13); // <- last register visible in RegAlloc
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DEBUG_ONLY(unallocated++); map_register(11, Z_R0); // Z_R0_scratch
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DEBUG_ONLY(unallocated++); map_register(12, Z_R1); // Z_R1_scratch
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DEBUG_ONLY(unallocated++); map_register(10, Z_R14); // return pc; TODO: Try to let c1/c2 allocate R14.
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// The following registers are usually unavailable.
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DEBUG_ONLY(unallocated++); map_register(13, Z_R8);
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DEBUG_ONLY(unallocated++); map_register(14, Z_R9);
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DEBUG_ONLY(unallocated++); map_register(15, Z_R15);
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assert(allocated-1 == pd_last_cpu_reg, "wrong number/mapping of allocated CPU registers");
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assert(unallocated == pd_nof_cpu_regs_unallocated, "wrong number of unallocated CPU registers");
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assert(nof_cpu_regs == allocated+unallocated, "wrong number of CPU registers");
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int j = 0;
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for (int i = 0; i < nof_fpu_regs; i++) {
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if (as_FloatRegister(i) == Z_fscratch_1) continue; // unallocated
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map_float_register(j++, as_FloatRegister(i));
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}
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assert(j == nof_fpu_regs-1, "missed one fpu reg?");
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map_float_register(j++, Z_fscratch_1);
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_init_done = true;
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Z_R0_opr = as_opr(Z_R0);
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Z_R1_opr = as_opr(Z_R1);
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Z_R2_opr = as_opr(Z_R2);
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Z_R3_opr = as_opr(Z_R3);
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Z_R4_opr = as_opr(Z_R4);
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Z_R5_opr = as_opr(Z_R5);
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Z_R6_opr = as_opr(Z_R6);
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Z_R7_opr = as_opr(Z_R7);
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Z_R8_opr = as_opr(Z_R8);
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Z_R9_opr = as_opr(Z_R9);
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Z_R10_opr = as_opr(Z_R10);
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Z_R11_opr = as_opr(Z_R11);
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Z_R12_opr = as_opr(Z_R12);
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Z_R13_opr = as_opr(Z_R13);
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Z_R14_opr = as_opr(Z_R14);
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Z_R15_opr = as_opr(Z_R15);
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Z_R0_oop_opr = as_oop_opr(Z_R0);
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Z_R1_oop_opr = as_oop_opr(Z_R1);
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Z_R2_oop_opr = as_oop_opr(Z_R2);
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Z_R3_oop_opr = as_oop_opr(Z_R3);
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Z_R4_oop_opr = as_oop_opr(Z_R4);
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Z_R5_oop_opr = as_oop_opr(Z_R5);
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Z_R6_oop_opr = as_oop_opr(Z_R6);
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Z_R7_oop_opr = as_oop_opr(Z_R7);
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Z_R8_oop_opr = as_oop_opr(Z_R8);
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Z_R9_oop_opr = as_oop_opr(Z_R9);
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Z_R10_oop_opr = as_oop_opr(Z_R10);
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Z_R11_oop_opr = as_oop_opr(Z_R11);
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Z_R12_oop_opr = as_oop_opr(Z_R12);
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Z_R13_oop_opr = as_oop_opr(Z_R13);
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Z_R14_oop_opr = as_oop_opr(Z_R14);
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Z_R15_oop_opr = as_oop_opr(Z_R15);
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Z_R0_metadata_opr = as_metadata_opr(Z_R0);
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Z_R1_metadata_opr = as_metadata_opr(Z_R1);
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Z_R2_metadata_opr = as_metadata_opr(Z_R2);
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Z_R3_metadata_opr = as_metadata_opr(Z_R3);
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Z_R4_metadata_opr = as_metadata_opr(Z_R4);
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Z_R5_metadata_opr = as_metadata_opr(Z_R5);
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Z_R6_metadata_opr = as_metadata_opr(Z_R6);
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Z_R7_metadata_opr = as_metadata_opr(Z_R7);
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Z_R8_metadata_opr = as_metadata_opr(Z_R8);
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Z_R9_metadata_opr = as_metadata_opr(Z_R9);
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Z_R10_metadata_opr = as_metadata_opr(Z_R10);
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Z_R11_metadata_opr = as_metadata_opr(Z_R11);
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Z_R12_metadata_opr = as_metadata_opr(Z_R12);
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Z_R13_metadata_opr = as_metadata_opr(Z_R13);
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Z_R14_metadata_opr = as_metadata_opr(Z_R14);
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Z_R15_metadata_opr = as_metadata_opr(Z_R15);
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// TODO: needed? Or can we make Z_R9 available for linear scan allocation.
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Z_FP_opr = as_pointer_opr(Z_fp);
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Z_SP_opr = as_pointer_opr(Z_SP);
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Z_R2_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R2), cpu_reg2rnr(Z_R2));
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Z_R10_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R10), cpu_reg2rnr(Z_R10));
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Z_R11_long_opr = LIR_OprFact::double_cpu(cpu_reg2rnr(Z_R11), cpu_reg2rnr(Z_R11));
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Z_F0_opr = as_float_opr(Z_F0);
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Z_F0_double_opr = as_double_opr(Z_F0);
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// All allocated cpu regs are caller saved.
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for (int c1rnr = 0; c1rnr < max_nof_caller_save_cpu_regs; c1rnr++) {
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_caller_save_cpu_regs[c1rnr] = as_opr(cpu_rnr2reg(c1rnr));
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}
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// All allocated fpu regs are caller saved.
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for (int c1rnr = 0; c1rnr < nof_caller_save_fpu_regs; c1rnr++) {
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_caller_save_fpu_regs[c1rnr] = as_float_opr(nr2floatreg(c1rnr));
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}
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}
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Address FrameMap::make_new_address(ByteSize sp_offset) const {
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return Address(Z_SP, sp_offset);
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}
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VMReg FrameMap::fpu_regname (int n) {
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return nr2floatreg(n)->as_VMReg();
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}
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LIR_Opr FrameMap::stack_pointer() {
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return Z_SP_opr;
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}
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// JSR 292
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// On ZARCH_64, there is no need to save the SP, because neither
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// method handle intrinsics nor compiled lambda forms modify it.
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LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
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return LIR_OprFact::illegalOpr;
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}
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bool FrameMap::validate_frame() {
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return true;
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}
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