368 lines
12 KiB
Plaintext
368 lines
12 KiB
Plaintext
dnl Copyright (c) 2014, Red Hat Inc. All rights reserved.
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dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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dnl
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dnl This code is free software; you can redistribute it and/or modify it
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dnl under the terms of the GNU General Public License version 2 only, as
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dnl published by the Free Software Foundation.
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dnl
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dnl This code is distributed in the hope that it will be useful, but WITHOUT
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dnl ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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dnl FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl version 2 for more details (a copy is included in the LICENSE file that
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dnl accompanied this code).
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dnl
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dnl You should have received a copy of the GNU General Public License version
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dnl 2 along with this work; if not, write to the Free Software Foundation,
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dnl Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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dnl
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dnl Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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dnl or visit www.oracle.com if you need additional information or have any
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dnl questions.
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dnl
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dnl
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dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic
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dnl and shift patterns patterns used in aarch64.ad.
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dnl
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// BEGIN This section of the file is automatically generated. Do not edit --------------
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dnl
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define(`ORL2I', `ifelse($1,I,orL2I)')
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dnl
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define(`BASE_SHIFT_INSN',
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`
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instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
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iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
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immI src3, rFlagsReg cr) %{
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match(Set dst ($2$1 src1 ($4$1 src2 src3)));
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ins_cost(1.9 * INSN_COST);
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format %{ "$3 $dst, $src1, $src2, $5 $src3" %}
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ins_encode %{
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__ $3(as_Register($dst$$reg),
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as_Register($src1$$reg),
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as_Register($src2$$reg),
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Assembler::$5,
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$src3$$constant & ifelse($1,I,0x1f,0x3f));
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%}
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ins_pipe(ialu_reg_reg_shift);
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%}')dnl
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define(`BASE_INVERTED_INSN',
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`
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instruct $2$1_reg_not_reg(iReg$1NoSp dst,
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iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_M1 m1,
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rFlagsReg cr) %{
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dnl This ifelse is because hotspot reassociates (xor (xor ..)..)
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dnl into this canonical form.
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ifelse($2,Xor,
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match(Set dst (Xor$1 m1 (Xor$1 src2 src1)));,
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match(Set dst ($2$1 src1 (Xor$1 src2 m1)));)
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ins_cost(INSN_COST);
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format %{ "$3 $dst, $src1, $src2" %}
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ins_encode %{
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__ $3(as_Register($dst$$reg),
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as_Register($src1$$reg),
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as_Register($src2$$reg),
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Assembler::LSL, 0);
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%}
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ins_pipe(ialu_reg_reg);
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%}')dnl
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define(`INVERTED_SHIFT_INSN',
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`
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instruct $2$1_reg_$4_not_reg(iReg$1NoSp dst,
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iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
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immI src3, imm$1_M1 src4, rFlagsReg cr) %{
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dnl This ifelse is because hotspot reassociates (xor (xor ..)..)
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dnl into this canonical form.
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ifelse($2,Xor,
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match(Set dst ($2$1 src4 (Xor$1($4$1 src2 src3) src1)));,
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match(Set dst ($2$1 src1 (Xor$1($4$1 src2 src3) src4)));)
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ins_cost(1.9 * INSN_COST);
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format %{ "$3 $dst, $src1, $src2, $5 $src3" %}
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ins_encode %{
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__ $3(as_Register($dst$$reg),
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as_Register($src1$$reg),
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as_Register($src2$$reg),
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Assembler::$5,
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$src3$$constant & ifelse($1,I,0x1f,0x3f));
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%}
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ins_pipe(ialu_reg_reg_shift);
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%}')dnl
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define(`NOT_INSN',
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`instruct reg$1_not_reg(iReg$1NoSp dst,
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iReg$1`'ORL2I($1) src1, imm$1_M1 m1,
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rFlagsReg cr) %{
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match(Set dst (Xor$1 src1 m1));
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ins_cost(INSN_COST);
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format %{ "$2 $dst, $src1, zr" %}
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ins_encode %{
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__ $2(as_Register($dst$$reg),
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as_Register($src1$$reg),
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zr,
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Assembler::LSL, 0);
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%}
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ins_pipe(ialu_reg);
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%}')dnl
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dnl
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define(`BOTH_SHIFT_INSNS',
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`BASE_SHIFT_INSN(I, $1, ifelse($2,andr,andw,$2w), $3, $4)
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BASE_SHIFT_INSN(L, $1, $2, $3, $4)')dnl
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dnl
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define(`BOTH_INVERTED_INSNS',
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`BASE_INVERTED_INSN(I, $1, $2w, $3, $4)
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BASE_INVERTED_INSN(L, $1, $2, $3, $4)')dnl
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dnl
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define(`BOTH_INVERTED_SHIFT_INSNS',
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`INVERTED_SHIFT_INSN(I, $1, $2w, $3, $4, ~0, int)
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INVERTED_SHIFT_INSN(L, $1, $2, $3, $4, ~0l, long)')dnl
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dnl
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define(`ALL_SHIFT_KINDS',
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`BOTH_SHIFT_INSNS($1, $2, URShift, LSR)
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BOTH_SHIFT_INSNS($1, $2, RShift, ASR)
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BOTH_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
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dnl
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define(`ALL_INVERTED_SHIFT_KINDS',
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`BOTH_INVERTED_SHIFT_INSNS($1, $2, URShift, LSR)
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BOTH_INVERTED_SHIFT_INSNS($1, $2, RShift, ASR)
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BOTH_INVERTED_SHIFT_INSNS($1, $2, LShift, LSL)')dnl
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dnl
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NOT_INSN(L, eon)
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NOT_INSN(I, eonw)
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BOTH_INVERTED_INSNS(And, bic)
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BOTH_INVERTED_INSNS(Or, orn)
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BOTH_INVERTED_INSNS(Xor, eon)
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ALL_INVERTED_SHIFT_KINDS(And, bic)
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ALL_INVERTED_SHIFT_KINDS(Xor, eon)
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ALL_INVERTED_SHIFT_KINDS(Or, orn)
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ALL_SHIFT_KINDS(And, andr)
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ALL_SHIFT_KINDS(Xor, eor)
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ALL_SHIFT_KINDS(Or, orr)
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ALL_SHIFT_KINDS(Add, add)
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ALL_SHIFT_KINDS(Sub, sub)
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dnl
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dnl EXTEND mode, rshift_op, src, lshift_count, rshift_count
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define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)')
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define(`BFM_INSN',`
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// Shift Left followed by Shift Right.
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// This idiom is used by the compiler for the i2b bytecode etc.
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instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rshift_count)
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%{
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match(Set dst EXTEND($1, $3, src, lshift_count, rshift_count));
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// Make sure we are not going to exceed what $4 can do.
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predicate((unsigned int)n->in(2)->get_int() <= $2
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&& (unsigned int)n->in(1)->in(2)->get_int() <= $2);
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ins_cost(INSN_COST * 2);
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format %{ "$4 $dst, $src, $rshift_count - $lshift_count, #$2 - $lshift_count" %}
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ins_encode %{
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int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;
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int s = $2 - lshift;
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int r = (rshift - lshift) & $2;
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__ $4(as_Register($dst$$reg),
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as_Register($src$$reg),
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r, s);
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%}
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ins_pipe(ialu_reg_shift);
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%}')
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BFM_INSN(L, 63, RShift, sbfm)
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BFM_INSN(I, 31, RShift, sbfmw)
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BFM_INSN(L, 63, URShift, ubfm)
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BFM_INSN(I, 31, URShift, ubfmw)
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dnl
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// Bitfield extract with shift & mask
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define(`BFX_INSN',
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`instruct $3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI rshift, imm$1_bitmask mask)
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%{
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match(Set dst (And$1 ($2$1 src rshift) mask));
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ins_cost(INSN_COST);
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format %{ "$3 $dst, $src, $mask" %}
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ins_encode %{
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int rshift = $rshift$$constant;
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long mask = $mask$$constant;
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int width = exact_log2(mask+1);
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__ $3(as_Register($dst$$reg),
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as_Register($src$$reg), rshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}')
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BFX_INSN(I,URShift,ubfxw)
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BFX_INSN(L,URShift,ubfx)
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// We can use ubfx when extending an And with a mask when we know mask
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// is positive. We know that because immI_bitmask guarantees it.
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instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
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%{
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match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
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ins_cost(INSN_COST * 2);
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format %{ "ubfx $dst, $src, $mask" %}
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ins_encode %{
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int rshift = $rshift$$constant;
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long mask = $mask$$constant;
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int width = exact_log2(mask+1);
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__ ubfx(as_Register($dst$$reg),
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as_Register($src$$reg), rshift, width);
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%}
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ins_pipe(ialu_reg_shift);
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%}
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// Rotations
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define(`EXTRACT_INSN',
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`instruct extr$3$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI lshift, immI rshift, rFlagsReg cr)
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%{
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match(Set dst ($3$1 (LShift$1 src1 lshift) (URShift$1 src2 rshift)));
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predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & $2));
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ins_cost(INSN_COST);
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format %{ "extr $dst, $src1, $src2, #$rshift" %}
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ins_encode %{
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__ $4(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
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$rshift$$constant & $2);
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%}
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ins_pipe(ialu_reg_reg_extr);
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%}
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')dnl
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EXTRACT_INSN(L, 63, Or, extr)
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EXTRACT_INSN(I, 31, Or, extrw)
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EXTRACT_INSN(L, 63, Add, extr)
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EXTRACT_INSN(I, 31, Add, extrw)
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define(`ROL_EXPAND', `
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// $2 expander
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instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
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%{
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effect(DEF dst, USE src, USE shift);
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format %{ "$2 $dst, $src, $shift" %}
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ins_cost(INSN_COST * 3);
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ins_encode %{
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__ subw(rscratch1, zr, as_Register($shift$$reg));
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__ $3(as_Register($dst$$reg), as_Register($src$$reg),
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rscratch1);
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%}
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ins_pipe(ialu_reg_reg_vshift);
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%}')dnl
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define(`ROR_EXPAND', `
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// $2 expander
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instruct $2$1_rReg(iReg$1NoSp dst, iReg$1 src, iRegI shift, rFlagsReg cr)
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%{
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effect(DEF dst, USE src, USE shift);
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format %{ "$2 $dst, $src, $shift" %}
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ins_cost(INSN_COST);
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ins_encode %{
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__ $3(as_Register($dst$$reg), as_Register($src$$reg),
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as_Register($shift$$reg));
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%}
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ins_pipe(ialu_reg_reg_vshift);
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%}')dnl
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define(ROL_INSN, `
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instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
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%{
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match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
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expand %{
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$3L_rReg(dst, src, shift, cr);
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%}
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%}')dnl
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define(ROR_INSN, `
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instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
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%{
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match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
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expand %{
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$3L_rReg(dst, src, shift, cr);
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%}
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%}')dnl
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ROL_EXPAND(L, rol, rorv)
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ROL_EXPAND(I, rol, rorvw)
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ROL_INSN(L, _64, rol)
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ROL_INSN(L, 0, rol)
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ROL_INSN(I, _32, rol)
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ROL_INSN(I, 0, rol)
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ROR_EXPAND(L, ror, rorv)
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ROR_EXPAND(I, ror, rorvw)
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ROR_INSN(L, _64, ror)
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ROR_INSN(L, 0, ror)
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ROR_INSN(I, _32, ror)
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ROR_INSN(I, 0, ror)
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// Add/subtract (extended)
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dnl ADD_SUB_EXTENDED(mode, size, add node, shift node, insn, shift type, wordsize
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define(`ADD_SUB_CONV', `
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instruct $3Ext$1(iReg$2NoSp dst, iReg$2`'ORL2I($2) src1, iReg$1`'ORL2I($1) src2, rFlagsReg cr)
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%{
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match(Set dst ($3$2 src1 (ConvI2L src2)));
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ins_cost(INSN_COST);
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format %{ "$4 $dst, $src1, $5 $src2" %}
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ins_encode %{
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__ $4(as_Register($dst$$reg), as_Register($src1$$reg),
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as_Register($src2$$reg), ext::$5);
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%}
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ins_pipe(ialu_reg_reg);
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%}')dnl
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ADD_SUB_CONV(I,L,Add,add,sxtw);
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ADD_SUB_CONV(I,L,Sub,sub,sxtw);
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dnl
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define(`ADD_SUB_EXTENDED', `
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instruct $3Ext$1_$6(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immI_`'eval($7-$2) lshift, immI_`'eval($7-$2) rshift, rFlagsReg cr)
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%{
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match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
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ins_cost(INSN_COST);
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format %{ "$5 $dst, $src1, $6 $src2" %}
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ins_encode %{
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__ $5(as_Register($dst$$reg), as_Register($src1$$reg),
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as_Register($src2$$reg), ext::$6);
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%}
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ins_pipe(ialu_reg_reg);
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%}')
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ADD_SUB_EXTENDED(I,16,Add,RShift,add,sxth,32)
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ADD_SUB_EXTENDED(I,8,Add,RShift,add,sxtb,32)
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ADD_SUB_EXTENDED(I,8,Add,URShift,add,uxtb,32)
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ADD_SUB_EXTENDED(L,16,Add,RShift,add,sxth,64)
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ADD_SUB_EXTENDED(L,32,Add,RShift,add,sxtw,64)
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ADD_SUB_EXTENDED(L,8,Add,RShift,add,sxtb,64)
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ADD_SUB_EXTENDED(L,8,Add,URShift,add,uxtb,64)
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dnl
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dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, shift type)
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define(`ADD_SUB_ZERO_EXTEND', `
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instruct $3Ext$1_$5_and(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, rFlagsReg cr)
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%{
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match(Set dst ($3$1 src1 (And$1 src2 mask)));
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ins_cost(INSN_COST);
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format %{ "$4 $dst, $src1, $src2, $5" %}
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ins_encode %{
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__ $4(as_Register($dst$$reg), as_Register($src1$$reg),
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as_Register($src2$$reg), ext::$5);
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%}
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ins_pipe(ialu_reg_reg);
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%}')
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dnl
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ADD_SUB_ZERO_EXTEND(I,255,Add,addw,uxtb)
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ADD_SUB_ZERO_EXTEND(I,65535,Add,addw,uxth)
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ADD_SUB_ZERO_EXTEND(L,255,Add,add,uxtb)
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ADD_SUB_ZERO_EXTEND(L,65535,Add,add,uxth)
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ADD_SUB_ZERO_EXTEND(L,4294967295,Add,add,uxtw)
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dnl
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ADD_SUB_ZERO_EXTEND(I,255,Sub,subw,uxtb)
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ADD_SUB_ZERO_EXTEND(I,65535,Sub,subw,uxth)
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ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb)
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ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
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ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
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// END This section of the file is automatically generated. Do not edit --------------
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