325 lines
14 KiB
C++
325 lines
14 KiB
C++
/*
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* Copyright (c) 2018, Intel Corporation.
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*
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#include "precompiled.hpp"
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#include "asm/assembler.hpp"
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#include "asm/assembler.inline.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "macroAssembler_x86.hpp"
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#ifdef _LP64
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// Multiply 128 x 128 bits, using 4 pclmulqdq operations
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void MacroAssembler::schoolbookAAD(int i, Register htbl, XMMRegister data,
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XMMRegister tmp0, XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3) {
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movdqu(xmm15, Address(htbl, i * 16));
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vpclmulhqlqdq(tmp3, data, xmm15); // 0x01
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vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);
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vpclmulldq(tmp3, data, xmm15); // 0x00
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vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit);
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vpclmulhdq(tmp3, data, xmm15); // 0x11
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vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit);
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vpclmullqhqdq(tmp3, data, xmm15); // 0x10
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vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);
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}
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// Multiply two 128 bit numbers resulting in a 256 bit value
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// Result of the multiplication followed by reduction stored in state
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void MacroAssembler::gfmul(XMMRegister tmp0, XMMRegister state) {
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const XMMRegister tmp1 = xmm4;
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const XMMRegister tmp2 = xmm5;
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const XMMRegister tmp3 = xmm6;
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const XMMRegister tmp4 = xmm7;
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vpclmulldq(tmp1, state, tmp0); //0x00 (a0 * b0)
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vpclmulhdq(tmp4, state, tmp0);//0x11 (a1 * b1)
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vpclmullqhqdq(tmp2, state, tmp0);//0x10 (a1 * b0)
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vpclmulhqlqdq(tmp3, state, tmp0); //0x01 (a0 * b1)
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vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit); // (a0 * b1) + (a1 * b0)
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vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit);
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vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit);
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vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit); // tmp1 and tmp4 hold the result
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vpxor(tmp4, tmp4, tmp2, Assembler::AVX_128bit); // of carryless multiplication
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// Follows the reduction technique mentioned in
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// Shift-XOR reduction described in Gueron-Kounavis May 2010
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// First phase of reduction
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//
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vpslld(xmm8, tmp1, 31, Assembler::AVX_128bit); // packed right shift shifting << 31
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vpslld(xmm9, tmp1, 30, Assembler::AVX_128bit); // packed right shift shifting << 30
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vpslld(xmm10, tmp1, 25, Assembler::AVX_128bit);// packed right shift shifting << 25
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// xor the shifted versions
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vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit);
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vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit);
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vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit);
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vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit);
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vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit);// first phase of the reduction complete
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//
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// Second phase of the reduction
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//
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vpsrld(xmm9, tmp1, 1, Assembler::AVX_128bit);// packed left shifting >> 1
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vpsrld(xmm10, tmp1, 2, Assembler::AVX_128bit);// packed left shifting >> 2
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vpsrld(xmm11, tmp1, 7, Assembler::AVX_128bit);// packed left shifting >> 7
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vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit);// xor the shifted versions
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vpxor(xmm9, xmm9, xmm11, Assembler::AVX_128bit);
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vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit);
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vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit);
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vpxor(state, tmp4, tmp1, Assembler::AVX_128bit);// the result is in state
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ret(0);
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}
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// This method takes the subkey after expansion as input and generates 1 * 16 power of subkey H.
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// The power of H is used in reduction process for one block ghash
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void MacroAssembler::generateHtbl_one_block(Register htbl) {
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const XMMRegister t = xmm13;
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// load the original subkey hash
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movdqu(t, Address(htbl, 0));
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// shuffle using long swap mask
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movdqu(xmm10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
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vpshufb(t, t, xmm10, Assembler::AVX_128bit);
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// Compute H' = GFMUL(H, 2)
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vpsrld(xmm3, t, 7, Assembler::AVX_128bit);
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movdqu(xmm4, ExternalAddress(StubRoutines::x86::ghash_shufflemask_addr()));
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vpshufb(xmm3, xmm3, xmm4, Assembler::AVX_128bit);
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movl(rax, 0xff00);
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movdl(xmm4, rax);
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vpshufb(xmm4, xmm4, xmm3, Assembler::AVX_128bit);
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movdqu(xmm5, ExternalAddress(StubRoutines::x86::ghash_polynomial_addr()));
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vpand(xmm5, xmm5, xmm4, Assembler::AVX_128bit);
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vpsrld(xmm3, t, 31, Assembler::AVX_128bit);
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vpslld(xmm4, t, 1, Assembler::AVX_128bit);
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vpslldq(xmm3, xmm3, 4, Assembler::AVX_128bit);
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vpxor(t, xmm4, xmm3, Assembler::AVX_128bit);// t holds p(x) <<1 or H * 2
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//Adding p(x)<<1 to xmm5 which holds the reduction polynomial
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vpxor(t, t, xmm5, Assembler::AVX_128bit);
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movdqu(Address(htbl, 1 * 16), t); // H * 2
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ret(0);
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}
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// This method takes the subkey after expansion as input and generates the remaining powers of subkey H.
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// The power of H is used in reduction process for eight block ghash
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void MacroAssembler::generateHtbl_eight_blocks(Register htbl) {
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const XMMRegister t = xmm13;
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const XMMRegister tmp0 = xmm1;
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Label GFMUL;
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movdqu(t, Address(htbl, 1 * 16));
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movdqu(tmp0, t);
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// tmp0 and t hold H. Now we compute powers of H by using GFMUL(H, H)
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 2 * 16), t); //H ^ 2 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 3 * 16), t); //H ^ 3 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 4 * 16), t); //H ^ 4 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 5 * 16), t); //H ^ 5 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 6 * 16), t); //H ^ 6 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 7 * 16), t); //H ^ 7 * 2
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call(GFMUL, relocInfo::none);
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movdqu(Address(htbl, 8 * 16), t); //H ^ 8 * 2
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ret(0);
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bind(GFMUL);
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gfmul(tmp0, t);
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}
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// Multiblock and single block GHASH computation using Shift XOR reduction technique
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void MacroAssembler::avx_ghash(Register input_state, Register htbl,
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Register input_data, Register blocks) {
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// temporary variables to hold input data and input state
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const XMMRegister data = xmm1;
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const XMMRegister state = xmm0;
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// temporary variables to hold intermediate results
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const XMMRegister tmp0 = xmm3;
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const XMMRegister tmp1 = xmm4;
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const XMMRegister tmp2 = xmm5;
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const XMMRegister tmp3 = xmm6;
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// temporary variables to hold byte and long swap masks
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const XMMRegister bswap_mask = xmm2;
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const XMMRegister lswap_mask = xmm14;
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Label GENERATE_HTBL_1_BLK, GENERATE_HTBL_8_BLKS, BEGIN_PROCESS, GFMUL, BLOCK8_REDUCTION,
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ONE_BLK_INIT, PROCESS_1_BLOCK, PROCESS_8_BLOCKS, SAVE_STATE, EXIT_GHASH;
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testptr(blocks, blocks);
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jcc(Assembler::zero, EXIT_GHASH);
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// Check if Hashtable (1*16) has been already generated
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// For anything less than 8 blocks, we generate only the first power of H.
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movdqu(tmp2, Address(htbl, 1 * 16));
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ptest(tmp2, tmp2);
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jcc(Assembler::notZero, BEGIN_PROCESS);
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call(GENERATE_HTBL_1_BLK, relocInfo::none);
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// Shuffle the input state
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bind(BEGIN_PROCESS);
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movdqu(lswap_mask, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
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movdqu(state, Address(input_state, 0));
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vpshufb(state, state, lswap_mask, Assembler::AVX_128bit);
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cmpl(blocks, 8);
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jcc(Assembler::below, ONE_BLK_INIT);
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// If we have 8 blocks or more data, then generate remaining powers of H
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movdqu(tmp2, Address(htbl, 8 * 16));
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ptest(tmp2, tmp2);
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jcc(Assembler::notZero, PROCESS_8_BLOCKS);
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call(GENERATE_HTBL_8_BLKS, relocInfo::none);
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//Do 8 multiplies followed by a reduction processing 8 blocks of data at a time
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//Each block = 16 bytes.
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bind(PROCESS_8_BLOCKS);
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subl(blocks, 8);
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movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));
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movdqu(data, Address(input_data, 16 * 7));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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//Loading 1*16 as calculated powers of H required starts at that location.
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movdqu(xmm15, Address(htbl, 1 * 16));
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//Perform carryless multiplication of (H*2, data block #7)
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vpclmulhqlqdq(tmp2, data, xmm15);//a0 * b1
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vpclmulldq(tmp0, data, xmm15);//a0 * b0
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vpclmulhdq(tmp1, data, xmm15);//a1 * b1
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vpclmullqhqdq(tmp3, data, xmm15);//a1* b0
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vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);// (a0 * b1) + (a1 * b0)
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movdqu(data, Address(input_data, 16 * 6));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^2 * 2, data block #6)
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schoolbookAAD(2, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 5));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^3 * 2, data block #5)
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schoolbookAAD(3, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 4));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^4 * 2, data block #4)
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schoolbookAAD(4, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 3));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^5 * 2, data block #3)
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schoolbookAAD(5, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 2));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^6 * 2, data block #2)
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schoolbookAAD(6, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 1));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^7 * 2, data block #1)
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schoolbookAAD(7, htbl, data, tmp0, tmp1, tmp2, tmp3);
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movdqu(data, Address(input_data, 16 * 0));
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// xor data block#0 with input state before perfoming carry-less multiplication
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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vpxor(data, data, state, Assembler::AVX_128bit);
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// Perform carryless multiplication of (H^8 * 2, data block #0)
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schoolbookAAD(8, htbl, data, tmp0, tmp1, tmp2, tmp3);
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vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit);
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vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit);
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vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit);// tmp0, tmp1 contains aggregated results of
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vpxor(tmp1, tmp1, tmp2, Assembler::AVX_128bit);// the multiplication operation
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// we have the 2 128-bit partially accumulated multiplication results in tmp0:tmp1
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// with higher 128-bit in tmp1 and lower 128-bit in corresponding tmp0
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// Follows the reduction technique mentioned in
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// Shift-XOR reduction described in Gueron-Kounavis May 2010
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bind(BLOCK8_REDUCTION);
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// First Phase of the reduction
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vpslld(xmm8, tmp0, 31, Assembler::AVX_128bit); // packed right shifting << 31
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vpslld(xmm9, tmp0, 30, Assembler::AVX_128bit); // packed right shifting << 30
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vpslld(xmm10, tmp0, 25, Assembler::AVX_128bit); // packed right shifting << 25
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// xor the shifted versions
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vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit);
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vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit);
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vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit);
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vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit);
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vpxor(tmp0, tmp0, xmm9, Assembler::AVX_128bit); // first phase of reduction is complete
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// second phase of the reduction
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vpsrld(xmm9, tmp0, 1, Assembler::AVX_128bit); // packed left shifting >> 1
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vpsrld(xmm10, tmp0, 2, Assembler::AVX_128bit); // packed left shifting >> 2
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vpsrld(tmp2, tmp0, 7, Assembler::AVX_128bit); // packed left shifting >> 7
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// xor the shifted versions
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vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit);
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vpxor(xmm9, xmm9, tmp2, Assembler::AVX_128bit);
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vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit);
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vpxor(tmp0, xmm9, tmp0, Assembler::AVX_128bit);
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// Final result is in state
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vpxor(state, tmp0, tmp1, Assembler::AVX_128bit);
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lea(input_data, Address(input_data, 16 * 8));
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cmpl(blocks, 8);
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jcc(Assembler::below, ONE_BLK_INIT);
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jmp(PROCESS_8_BLOCKS);
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// Since this is one block operation we will only use H * 2 i.e. the first power of H
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bind(ONE_BLK_INIT);
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movdqu(tmp0, Address(htbl, 1 * 16));
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movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));
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//Do one (128 bit x 128 bit) carry-less multiplication at a time followed by a reduction.
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bind(PROCESS_1_BLOCK);
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cmpl(blocks, 0);
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jcc(Assembler::equal, SAVE_STATE);
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subl(blocks, 1);
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movdqu(data, Address(input_data, 0));
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vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
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vpxor(state, state, data, Assembler::AVX_128bit);
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// gfmul(H*2, state)
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call(GFMUL, relocInfo::none);
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addptr(input_data, 16);
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jmp(PROCESS_1_BLOCK);
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bind(SAVE_STATE);
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vpshufb(state, state, lswap_mask, Assembler::AVX_128bit);
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movdqu(Address(input_state, 0), state);
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jmp(EXIT_GHASH);
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bind(GFMUL);
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gfmul(tmp0, state);
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bind(GENERATE_HTBL_1_BLK);
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generateHtbl_one_block(htbl);
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bind(GENERATE_HTBL_8_BLKS);
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generateHtbl_eight_blocks(htbl);
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bind(EXIT_GHASH);
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// zero out xmm registers used for Htbl storage
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vpxor(xmm0, xmm0, xmm0, Assembler::AVX_128bit);
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vpxor(xmm1, xmm1, xmm1, Assembler::AVX_128bit);
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vpxor(xmm3, xmm3, xmm3, Assembler::AVX_128bit);
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vpxor(xmm15, xmm15, xmm15, Assembler::AVX_128bit);
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}
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#endif // _LP64
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