419 lines
14 KiB
C++
419 lines
14 KiB
C++
/*
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2019 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef OS_CPU_LINUX_PPC_ATOMIC_LINUX_PPC_HPP
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#define OS_CPU_LINUX_PPC_ATOMIC_LINUX_PPC_HPP
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#ifndef PPC64
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#error "Atomic currently only implemented for PPC64"
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#endif
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#include "orderAccess_linux_ppc.hpp"
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#include "utilities/debug.hpp"
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// Implementation of class atomic
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//
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// machine barrier instructions:
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//
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// - sync two-way memory barrier, aka fence
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// - lwsync orders Store|Store,
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// Load|Store,
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// Load|Load,
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// but not Store|Load
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// - eieio orders memory accesses for device memory (only)
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// - isync invalidates speculatively executed instructions
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// From the POWER ISA 2.06 documentation:
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// "[...] an isync instruction prevents the execution of
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// instructions following the isync until instructions
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// preceding the isync have completed, [...]"
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// From IBM's AIX assembler reference:
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// "The isync [...] instructions causes the processor to
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// refetch any instructions that might have been fetched
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// prior to the isync instruction. The instruction isync
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// causes the processor to wait for all previous instructions
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// to complete. Then any instructions already fetched are
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// discarded and instruction processing continues in the
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// environment established by the previous instructions."
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//
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// semantic barrier instructions:
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// (as defined in orderAccess.hpp)
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//
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// - release orders Store|Store, (maps to lwsync)
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// Load|Store
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// - acquire orders Load|Store, (maps to lwsync)
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// Load|Load
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// - fence orders Store|Store, (maps to sync)
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// Load|Store,
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// Load|Load,
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// Store|Load
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//
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inline void pre_membar(atomic_memory_order order) {
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switch (order) {
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case memory_order_relaxed:
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case memory_order_acquire: break;
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case memory_order_release:
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case memory_order_acq_rel: __asm__ __volatile__ ("lwsync" : : : "memory"); break;
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default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
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}
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}
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inline void post_membar(atomic_memory_order order) {
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switch (order) {
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case memory_order_relaxed:
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case memory_order_release: break;
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case memory_order_acquire:
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case memory_order_acq_rel: __asm__ __volatile__ ("isync" : : : "memory"); break;
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default /*conservative*/ : __asm__ __volatile__ ("sync" : : : "memory"); break;
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}
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}
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template<size_t byte_size>
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struct Atomic::PlatformAdd {
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template<typename D, typename I>
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D add_and_fetch(D volatile* dest, I add_value, atomic_memory_order order) const;
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template<typename D, typename I>
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D fetch_and_add(D volatile* dest, I add_value, atomic_memory_order order) const {
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return add_and_fetch(dest, add_value, order) - add_value;
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}
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};
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template<>
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template<typename D, typename I>
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inline D Atomic::PlatformAdd<4>::add_and_fetch(D volatile* dest, I add_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(4 == sizeof(I));
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STATIC_ASSERT(4 == sizeof(D));
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D result;
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pre_membar(order);
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__asm__ __volatile__ (
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"1: lwarx %0, 0, %2 \n"
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" add %0, %0, %1 \n"
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" stwcx. %0, 0, %2 \n"
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" bne- 1b \n"
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: /*%0*/"=&r" (result)
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: /*%1*/"r" (add_value), /*%2*/"r" (dest)
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: "cc", "memory" );
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post_membar(order);
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return result;
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}
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template<>
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template<typename D, typename I>
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inline D Atomic::PlatformAdd<8>::add_and_fetch(D volatile* dest, I add_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(8 == sizeof(I));
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STATIC_ASSERT(8 == sizeof(D));
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D result;
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pre_membar(order);
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__asm__ __volatile__ (
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"1: ldarx %0, 0, %2 \n"
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" add %0, %0, %1 \n"
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" stdcx. %0, 0, %2 \n"
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" bne- 1b \n"
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: /*%0*/"=&r" (result)
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: /*%1*/"r" (add_value), /*%2*/"r" (dest)
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: "cc", "memory" );
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post_membar(order);
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return result;
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}
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template<>
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template<typename T>
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inline T Atomic::PlatformXchg<4>::operator()(T volatile* dest,
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T exchange_value,
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atomic_memory_order order) const {
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// Note that xchg doesn't necessarily do an acquire
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// (see synchronizer.cpp).
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T old_value;
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const uint64_t zero = 0;
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pre_membar(order);
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__asm__ __volatile__ (
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/* atomic loop */
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"1: \n"
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" lwarx %[old_value], %[dest], %[zero] \n"
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" stwcx. %[exchange_value], %[dest], %[zero] \n"
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" bne- 1b \n"
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/* exit */
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"2: \n"
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/* out */
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: [old_value] "=&r" (old_value),
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"=m" (*dest)
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/* in */
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: [dest] "b" (dest),
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[zero] "r" (zero),
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[exchange_value] "r" (exchange_value),
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"m" (*dest)
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/* clobber */
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: "cc",
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"memory"
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);
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post_membar(order);
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return old_value;
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}
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template<>
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template<typename T>
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inline T Atomic::PlatformXchg<8>::operator()(T volatile* dest,
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T exchange_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(8 == sizeof(T));
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// Note that xchg doesn't necessarily do an acquire
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// (see synchronizer.cpp).
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T old_value;
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const uint64_t zero = 0;
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pre_membar(order);
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__asm__ __volatile__ (
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/* atomic loop */
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"1: \n"
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" ldarx %[old_value], %[dest], %[zero] \n"
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" stdcx. %[exchange_value], %[dest], %[zero] \n"
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" bne- 1b \n"
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/* exit */
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"2: \n"
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/* out */
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: [old_value] "=&r" (old_value),
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"=m" (*dest)
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/* in */
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: [dest] "b" (dest),
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[zero] "r" (zero),
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[exchange_value] "r" (exchange_value),
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"m" (*dest)
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/* clobber */
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: "cc",
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"memory"
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);
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post_membar(order);
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return old_value;
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}
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template<>
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template<typename T>
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inline T Atomic::PlatformCmpxchg<1>::operator()(T volatile* dest,
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T compare_value,
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T exchange_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(1 == sizeof(T));
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// Note that cmpxchg guarantees a two-way memory barrier across
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// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
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// specified otherwise (see atomic.hpp).
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// Using 32 bit internally.
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volatile int *dest_base = (volatile int*)((uintptr_t)dest & ~3);
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#ifdef VM_LITTLE_ENDIAN
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const unsigned int shift_amount = ((uintptr_t)dest & 3) * 8;
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#else
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const unsigned int shift_amount = ((~(uintptr_t)dest) & 3) * 8;
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#endif
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const unsigned int masked_compare_val = ((unsigned int)(unsigned char)compare_value),
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masked_exchange_val = ((unsigned int)(unsigned char)exchange_value),
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xor_value = (masked_compare_val ^ masked_exchange_val) << shift_amount;
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unsigned int old_value, value32;
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pre_membar(order);
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__asm__ __volatile__ (
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/* simple guard */
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" lbz %[old_value], 0(%[dest]) \n"
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" cmpw %[masked_compare_val], %[old_value] \n"
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" bne- 2f \n"
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/* atomic loop */
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"1: \n"
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" lwarx %[value32], 0, %[dest_base] \n"
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/* extract byte and compare */
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" srd %[old_value], %[value32], %[shift_amount] \n"
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" clrldi %[old_value], %[old_value], 56 \n"
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" cmpw %[masked_compare_val], %[old_value] \n"
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" bne- 2f \n"
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/* replace byte and try to store */
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" xor %[value32], %[xor_value], %[value32] \n"
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" stwcx. %[value32], 0, %[dest_base] \n"
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" bne- 1b \n"
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/* exit */
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"2: \n"
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/* out */
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: [old_value] "=&r" (old_value),
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[value32] "=&r" (value32),
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"=m" (*dest),
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"=m" (*dest_base)
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/* in */
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: [dest] "b" (dest),
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[dest_base] "b" (dest_base),
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[shift_amount] "r" (shift_amount),
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[masked_compare_val] "r" (masked_compare_val),
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[xor_value] "r" (xor_value),
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"m" (*dest),
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"m" (*dest_base)
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/* clobber */
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: "cc",
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"memory"
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);
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post_membar(order);
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return PrimitiveConversions::cast<T>((unsigned char)old_value);
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}
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template<>
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template<typename T>
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inline T Atomic::PlatformCmpxchg<4>::operator()(T volatile* dest,
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T compare_value,
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T exchange_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(4 == sizeof(T));
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// Note that cmpxchg guarantees a two-way memory barrier across
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// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
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// specified otherwise (see atomic.hpp).
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T old_value;
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const uint64_t zero = 0;
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pre_membar(order);
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__asm__ __volatile__ (
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/* simple guard */
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" lwz %[old_value], 0(%[dest]) \n"
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" cmpw %[compare_value], %[old_value] \n"
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" bne- 2f \n"
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/* atomic loop */
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"1: \n"
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" lwarx %[old_value], %[dest], %[zero] \n"
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" cmpw %[compare_value], %[old_value] \n"
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" bne- 2f \n"
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" stwcx. %[exchange_value], %[dest], %[zero] \n"
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" bne- 1b \n"
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/* exit */
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"2: \n"
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/* out */
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: [old_value] "=&r" (old_value),
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"=m" (*dest)
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/* in */
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: [dest] "b" (dest),
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[zero] "r" (zero),
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[compare_value] "r" (compare_value),
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[exchange_value] "r" (exchange_value),
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"m" (*dest)
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/* clobber */
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: "cc",
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"memory"
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);
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post_membar(order);
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return old_value;
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}
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template<>
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template<typename T>
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inline T Atomic::PlatformCmpxchg<8>::operator()(T volatile* dest,
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T compare_value,
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T exchange_value,
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atomic_memory_order order) const {
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STATIC_ASSERT(8 == sizeof(T));
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// Note that cmpxchg guarantees a two-way memory barrier across
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// the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
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// specified otherwise (see atomic.hpp).
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T old_value;
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const uint64_t zero = 0;
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pre_membar(order);
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__asm__ __volatile__ (
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/* simple guard */
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" ld %[old_value], 0(%[dest]) \n"
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" cmpd %[compare_value], %[old_value] \n"
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" bne- 2f \n"
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/* atomic loop */
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"1: \n"
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" ldarx %[old_value], %[dest], %[zero] \n"
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" cmpd %[compare_value], %[old_value] \n"
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" bne- 2f \n"
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" stdcx. %[exchange_value], %[dest], %[zero] \n"
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" bne- 1b \n"
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/* exit */
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"2: \n"
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/* out */
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: [old_value] "=&r" (old_value),
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"=m" (*dest)
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/* in */
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: [dest] "b" (dest),
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[zero] "r" (zero),
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[compare_value] "r" (compare_value),
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[exchange_value] "r" (exchange_value),
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"m" (*dest)
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/* clobber */
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: "cc",
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"memory"
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);
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post_membar(order);
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return old_value;
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}
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template<size_t byte_size>
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struct Atomic::PlatformOrderedLoad<byte_size, X_ACQUIRE>
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{
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template <typename T>
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T operator()(const volatile T* p) const {
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T t = Atomic::load(p);
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// Use twi-isync for load_acquire (faster than lwsync).
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__asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (t) : "memory");
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return t;
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}
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};
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#endif // OS_CPU_LINUX_PPC_ATOMIC_LINUX_PPC_HPP
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