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61 Commits

Author SHA1 Message Date
Christian Thalinger
9e981ee107 Merge 2015-12-18 12:39:02 -08:00
Vivek R Deshpande
2d9a6cfd3f 8143355: Update for addition of vectorizedMismatch intrinsic for x86 
Co-authored-by: Liqi Yi <liqi.yi@intel.com>
Reviewed-by: kvn
 2015-12-07 16:35:07 -08:00
Jon Masamitsu
e62c706965 8133023: ParallelGCThreads is not calculated correctly 
Reviewed-by: kbarrett, tschatzl, sangheki, dholmes
 2015-11-24 15:56:40 -08:00
Ahmed Khawaja
e28d9ba105 8143012: CRC32 Intrinsics support on SPARC 
Reviewed-by: kvn, roland
 2015-11-20 08:29:10 -08:00
Konstantin Shefov
6de50f10f5 8131778: java disables UseAES flag when using VIS=2 on sparc 
Reviewed-by: iignatyev, kvn
 2015-11-13 18:14:41 +03:00
Christian Thalinger
6896030b96 8140424: don't prefix developer and notproduct flag variables with CONST_ in product builds 
Reviewed-by: goetz, stefank
 2015-11-11 16:32:17 -10:00
Zoltan Majo
fc2a5e9d53 8078554: Compiler: implement ranges (optionally constraints) for those flags that have them missing 
Add range check or constraint where necessary.

Reviewed-by: roland, thartmann
 2015-10-09 14:21:26 +02:00
Jesper Wilhelmsson
1736e104a1 Merge 2015-09-08 16:10:37 +02:00
Ahmed Khawaja
d7b8032741 8132081: C2 support for Adler32 on SPARC 
Add C2 instrinsic support for Adler32 checksum on SPARC.

Reviewed-by: kvn
 2015-09-03 15:03:12 -07:00
Igor Veresov
20b11ddd88 8135035: Reverse changes from 8075093 
8075093 turn on FPU spilling that need to be stabilized first

Reviewed-by: kvn
 2015-09-03 14:29:08 -07:00
Kim Barrett
15196341a5 8131330: G1CollectedHeap::verify_dirty_young_list fails with assert 
Use assembly loop to avoid compiler optimization into memset

Reviewed-by: ecaspole, tschatzl
 2015-08-31 13:06:01 -04:00
Shrinivas Joshi
f10466290d 8075093: Enable UseFPUForSpilling support on SPARC 
Use single-cycle MOV instructions (MOVdTOx, MOVxTOd) for spills on SPARC which have them.

Reviewed-by: kvn
 2015-09-02 15:11:22 -07:00
Anthony Scarpino
2c695decc2 8131078: typos in ghash cpu message 
Reviewed-by: goetz, kvn
 2015-07-13 13:22:21 -07:00
Zoltan Majo
547a40e75a 8130120: Handling of SHA intrinsics inconsistent across platforms 
Introduce common warning message and common processing of SHA intrinsic-related arguments.

Reviewed-by: kvn, mcberg
 2015-07-03 09:33:04 +02:00
James Cheng
e2533553f6 8073583: C2 support for CRC32C on SPARC 
Reviewed-by: jrose, kvn
 2015-06-29 00:10:01 -07:00
Anthony Scarpino
c4c528df14 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration 
Reviewed-by: kvn, jrose
 2015-06-17 17:48:25 -07:00
Igor Veresov
1b5090da9e 8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect 
Chcek both l2-dcache-line-size and l2-cache-line-size properties to determine the size of the line

Reviewed-by: kvn
 2015-04-06 20:20:17 -07:00
Andrew Haley
1dfbc44c1f 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods 
Use unaligned Unsafe loads and stores for ByteBuffer access on platforms which support unaligned access. Add intrinsics for Unsafe.{get,put}-X-Unaligned methods.

Reviewed-by: dholmes, jrose, psandoz, kvn
 2015-03-31 12:31:18 -07:00
Igor Veresov
5db7b3a4e1 8056124: Hotspot should use PICL interface to get cacheline size on SPARC 
Using libpicl to get L1 data and L2 cache line sizes

Reviewed-by: kvn, roland, morris
 2014-09-05 11:23:47 -07:00
Zhengyu Gu
8a690a1250 6424123: JVM crashes on failed 'strdup' call 
Calling os::malloc()/os::strdup() and new os::strdup_check_oom() instead of ::malloc()/::strdup() for native memory tracking purpose

Reviewed-by: coleenp, ctornqvi, kvn
 2014-08-11 10:18:09 -07:00
Daniel D. Daugherty
a06d36cada 8049717: expose L1_data_cache_line_size for diagnostic/sanity checks 
Add support for VM_Version::L1_data_cache_line_size().

Reviewed-by: dsimms, kvn, dholmes
 2014-07-15 07:33:49 -07:00
Goetz Lindenmaier
f2051ed6fa 8048241: Introduce umbrella header os.inline.hpp and clean up includes 
Reviewed-by: coleenp, dholmes, lfoltan
 2014-06-26 16:05:15 +02:00
James Cheng
395560c428 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC 
Add C2 SHA intrinsics on SPARC

Reviewed-by: kvn, roland
 2014-06-11 11:05:10 -07:00
David Chase
305ec3bd3f 8037816: Fix for 8036122 breaks build with Xcode5/clang 
Repaired or selectively disabled offending formats; future-proofed with additional checking

Reviewed-by: kvn, jrose, stefank
 2014-05-09 16:50:54 -04:00
Shrinivas Joshi
c0f886ec65 8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc 
Fix the arbitrary alignment issue in SPARC AES crypto stub routines.

Reviewed-by: kvn, iveresov
 2014-04-30 14:14:01 -07:00
Shrinivas Joshi
d4c9d3889b 8002074: Support for AES on SPARC 
Add intrinsics/stub routines support for single-block and multi-block (as used by Cipher Block Chaining mode) AES encryption and decryption operations on the SPARC platform.

Reviewed-by: kvn, roland
 2014-01-14 17:46:48 -08:00
Mikael Vidstedt
a0da47fd66 8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013 
Copyright year updated for files modified during 2013

Reviewed-by: twisti, iveresov
 2013-12-24 11:48:39 -08:00
Volker Simonis
f0010291f7 8029190: VM_Version::determine_features() asserts on Fujitsu Sparc64 CPUs 
Fix code to allow testing on Fujitsu Sparc64 CPUs

Reviewed-by: kvn
 2013-12-02 11:12:32 +01:00
Morris Meyer
5b2339a7a2 8008407: remove SPARC V8 support 
Removed most of the SPARC V8 instructions

Reviewed-by: kvn, twisti
 2013-06-07 16:46:37 -07:00
Aleksey Shipilev
0614ed6542 8003985: Support @Contended Annotation - JEP 142 
HotSpot changes to support @Contended annotation.

Reviewed-by: coleenp, kvn, jrose
 2013-01-14 15:17:47 +01:00
Christian Thalinger
34733bb83c 8003250: SPARC: move MacroAssembler into separate file 
Reviewed-by: jrose, kvn
 2012-12-06 09:57:41 -08:00
Roland Westrelin
61eb5a0549 7054512: Compress class pointers after perm gen removal 
Support of compress class pointers in the compilers.

Reviewed-by: kvn, twisti
 2012-10-09 10:11:38 +02:00
Tao Mao
c791cfaf95 7188176: The JVM should differentiate between T and M series and adjust GC ergonomics 
Reviewed-by: kvn
 2012-09-24 11:07:03 -07:00
Roland Westrelin
302540691b 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() 
Use shorter instruction sequences for atomic add and atomic exchange when possible.

Reviewed-by: kvn, jrose
 2012-09-20 16:49:17 +02:00
John Cuthbertson
384650cb3e 7192128: G1: Extend fix for 6948537 to G1's BOT 
G1 does not appear to be immune to the issue described in CR 6948537 and increasing the size of old-generation PLABs appears to increase the liklihood of seeing the issue. Extend the fix for 6948537 to G1's BlockOffsetTable.

Reviewed-by: brutisso, jmasa
 2012-08-21 10:05:57 -07:00
Vladimir Kozlov
d1191bb4f4 7119644: Increase superword's vector size up to 256 bits 
Increase vector size up to 256-bits for YMM AVX registers on x86.

Reviewed-by: never, twisti, roland
 2012-06-15 01:25:19 -07:00
Christian Thalinger
5ffce97ffc 7104561: UseRDPCForConstantTableBase doesn't work after shorten branches changes 
Reviewed-by: never, kvn
 2011-10-31 03:06:42 -07:00
Vladimir Kozlov
f7d7a6071a 7039731: arraycopy could use prefetch on SPARC 
Use BIS and prefetch in arraycopy stubs for Sparc (BIS for T4 only).

Reviewed-by: never, iveresov
 2011-09-02 12:13:33 -07:00
Vladimir Kozlov
6446205688 7059037: Use BIS for zeroing on T4 
Use BIS for zeroing new allocated big (2Kb and more) objects and arrays.

Reviewed-by: never, twisti, ysr
 2011-08-26 08:52:22 -07:00
Vladimir Kozlov
90651b2666 7079329: Adjust allocation prefetching for T4 
On T4 2 BIS instructions should be issued to prefetch 64 bytes

Reviewed-by: iveresov, phh, twisti
 2011-08-16 16:59:46 -07:00
Vladimir Kozlov
ac99f413d7 7063629: use cbcond in C2 generated code on T4 
Use new short branch instruction in C2 generated code.

Reviewed-by: never
 2011-08-11 12:08:11 -07:00
Vladimir Kozlov
48c1293916 7063628: Use cbcond on T4 
Add new short branch instruction to Hotspot sparc assembler.

Reviewed-by: never, twisti, jrose
 2011-07-21 11:25:07 -07:00
Vladimir Kozlov
20a26c54cd 7059034: Use movxtod/movdtox on T4 
Use new VIS3 mov instructions on T4 for move data between general and float registers.

Reviewed-by: never, twisti
 2011-07-08 09:38:48 -07:00
Vladimir Kozlov
9fd396ce55 7006505: Use kstat info to identify SPARC processor 
Read Solaris kstat data to get more precise CPU information

Reviewed-by: iveresov, never, twisti, dholmes
 2010-12-16 14:15:12 -08:00
Stefan Karlsson
8006fe8f75 6989984: Use standard include model for Hospot 
Replaced MakeDeps and the includeDB files with more standardized solutions.

Reviewed-by: coleenp, kvn, kamg
 2010-11-23 13:22:55 -08:00
Vladimir Kozlov
249b1f6c4f 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14 
Use hardware DIV instruction for long division by constant when it is faster than code with multiply.

Reviewed-by: never
 2010-11-02 09:00:37 -07:00
Tom Rodriguez
a54b1ff70e 6978249: spill between cpu and fpu registers when those moves are fast 
Reviewed-by: kvn
 2010-08-19 14:51:47 -07:00
John R Rose
d6a9b93b5a Merge 2010-06-02 22:45:42 -07:00
Vladimir Kozlov
a3005a16fc 6954029: Improve implicit null check generation with compressed oops 
Hoist DecodeN instruction above null check

Reviewed-by: never, twisti
 2010-06-02 09:49:32 -07:00
Erik Trimble
ba7c173659 6941466: Oracle rebranding changes for Hotspot repositories 
Change all the Sun copyrights to Oracle copyright

Reviewed-by: ohair
 2010-05-27 19:08:38 -07:00