1155 Commits

Author SHA1 Message Date
Felix Yang
12cba200a3 8138583: aarch64: add support for vectorizing fabs/fneg
Reviewed-by: aph, roland
2015-09-30 04:35:39 -04:00
Andrew Haley
f44f56e351 8138575: Improve generated code for profile counters
Reviewed-by: kvn
2015-09-29 17:01:37 +00:00
Felix Yang
65cf3f8eed 8138641: Disable C2 peephole by default for aarch64
Reviewed-by: roland
2015-09-30 13:23:46 +00:00
Martin Doerr
71edab514c 8139421: PPC64LE: MacroAssembler::bxx64_patchable kill register R12
Register R12 must be preserved for stub calls (e.g. deopt handler).

Reviewed-by: goetz
2015-10-12 12:20:38 +02:00
Vivek R Deshpande
e4f225de72 8139454: java/lang/Math/WorstCaseTests.java crashes on Linux-amd64
Emit the form of pextrw that works with sse2

Reviewed-by: iveresov, twisti
2015-10-12 16:35:40 -07:00
Zoltan Majo
fc2a5e9d53 8078554: Compiler: implement ranges (optionally constraints) for those flags that have them missing
Add range check or constraint where necessary.

Reviewed-by: roland, thartmann
2015-10-09 14:21:26 +02:00
Dean Long
9bb4c7872b Merge 2015-10-09 02:43:50 -04:00
Christian Thalinger
16526e000e 8136421: JEP 243: Java-Level JVM Compiler Interface
Reviewed-by: ihse, alanb, roland, coleenp, iveresov, kvn, kbarrett
2015-10-08 12:49:30 -10:00
David Lindholm
1e71f67736 8080775: Better argument formatting for assert() and friends
Reviewed-by: kbarrett, pliden
2015-09-29 11:02:08 +02:00
Andrew Haley
67af37e0b8 8135018: AARCH64: Missing memory barriers for CMS collector
Add StoreStore barrier when CMS needs them

Reviewed-by: tschatzl
2015-09-24 12:04:57 +02:00
Ed Nevill
cb8cff7e6e 8135231: aarch64: add support for vectorizing double precision sqrt
Reviewed-by: roland, aph
2015-09-23 12:39:30 -04:00
Andrew Haley
660dad780b 8136165: AARCH64: Tidy up compiled native calls
Do some cleaning

Reviewed-by: roland, kvn, enevill
2015-09-28 16:18:15 +00:00
Igor Veresov
74519e1e1a Merge 2015-09-25 12:04:35 -07:00
Jesper Wilhelmsson
7f7b300f89 Merge 2015-09-21 17:49:57 +02:00
Roland Westrelin
f8abd0e843 8136820: Generate better code for some Unsafe addressing patterns
Reshape address computation to move invariant part out of loops

Reviewed-by: kvn
2015-09-17 16:53:42 +02:00
Ed Nevill
050184d76f 8136615: aarch64: elide DecodeN when followed by CmpP 0
Remove DecodeN when comparing a narrow oop with 0

Reviewed-by: kvn, adinn
2015-09-16 13:50:57 +00:00
Andrew Dinn
1a53878451 8080293: AARCH64: Remove unnecessary dmbs from generated CAS code
The current encoding for CAS generates unnecessary leading and trailing dmbs for the MemBarAcquire and MemBarRelease which ought to be elided

Reviewed-by: kvn
2015-09-16 09:52:58 -04:00
Martin Doerr
99c37e9ee2 8136525: Generate interpreter entries only once and avoid unnecessary jump to jump
Reviewed-by: coleenp, twisti, aph
2015-09-17 09:03:57 +02:00
Tomasz Wojtowicz
61b77b8590 8134553: CRC32C implementations for x86/x64 targets
Reviewed-by: kvn
2015-09-16 15:54:32 -07:00
Michael Berg
d49d1ea740 8134802: LCM register pressure scheduling
Calculate register pressure in a block to help instructions scheduling.

Reviewed-by: kvn, dlong
2015-09-16 13:16:17 -07:00
Felix Yang
00a6ff7050 8136524: aarch64: test/compiler/runtime/7196199/Test7196199.java fails
Fix safepoint handlers to save 128 bits on vector poll

Reviewed-by: kvn
2015-09-15 12:59:51 +00:00
Aleksey Shipilev
bbc043a7f2 8135085: Change Method::_intrinsic_id from u1 to u2
Convert Method::_intrinsic_id from u1 to u2 to expand id range over 255.

Reviewed-by: coleenp, iklam, jiangli
2015-09-18 13:41:11 -07:00
Michael Berg
d67924dc8e 8132160: support for AVX 512 call frames and stack management
Simplify save/restore frame on x86 systems which support EVEX.

Reviewed-by: kvn, iveresov
2015-09-11 17:02:44 -07:00
Jesper Wilhelmsson
1736e104a1 Merge 2015-09-08 16:10:37 +02:00
Andrew Haley
518c5cacbc 8135157: DMB elimination in AArch64 C2 synchronization implementation
Reduce memory barrier usage in C2 fast lock and unlock.

Co-authored-by: Wei Tang <wei.tang@linaro.org>
Reviewed-by: kvn
2015-09-08 14:08:58 +01:00
Igor Veresov
e88940fae6 Merge 2015-09-10 17:56:43 -07:00
Michael Berg
e75f5a5cde 8135028: support for vectorizing double precision sqrt
Reviewed-by: kvn, twisti
2015-09-09 10:34:17 -07:00
Ahmed Khawaja
d7b8032741 8132081: C2 support for Adler32 on SPARC
Add C2 instrinsic support for Adler32 checksum on SPARC.

Reviewed-by: kvn
2015-09-03 15:03:12 -07:00
Igor Veresov
20b11ddd88 8135035: Reverse changes from 8075093
8075093 turn on FPU spilling that need to be stabilized first

Reviewed-by: kvn
2015-09-03 14:29:08 -07:00
Dmitry Samersoff
21b8f01e4e Merge 2015-08-31 23:29:02 +02:00
Dmitry Samersoff
6ed285af0a Merge 2015-08-31 21:46:33 +03:00
Kim Barrett
15196341a5 8131330: G1CollectedHeap::verify_dirty_young_list fails with assert
Use assembly loop to avoid compiler optimization into memset

Reviewed-by: ecaspole, tschatzl
2015-08-31 13:06:01 -04:00
Shrinivas Joshi
f10466290d 8075093: Enable UseFPUForSpilling support on SPARC
Use single-cycle MOV instructions (MOVdTOx, MOVxTOd) for spills on SPARC which have them.

Reviewed-by: kvn
2015-09-02 15:11:22 -07:00
Andrew Haley
ef62a6daab 8134869: AARCH64: GHASH intrinsic is not optimal
Rewrite intrinsic to make better use of SIMD instructions

Reviewed-by: kvn
2015-09-02 13:23:59 +00:00
Hui Shi
3b19bff980 8134322: AArch64: Fix several errors in C2 biased locking implementation
Several errors in C2 biased locking require fixing

Reviewed-by: kvn
2015-08-26 17:13:59 +01:00
Roland Westrelin
a9e232a8ef Merge 2015-08-21 09:12:42 +02:00
Ed Nevill
10c3342331 8133842: aarch64: C2 generates illegal instructions with int shifts >=32
Fix logical operatations combined with shifts >= 32

Reviewed-by: kvn, aph, adinn
2015-08-20 09:40:08 +00:00
Kim Barrett
7706e36194 8072817: CardTableExtension kind() should be BarrierSet::CardTableExtension
Use BarrierSet::CardTableForRS where needed, and update concrete bs tags.

Reviewed-by: jwilhelm, jmasa
2015-08-18 17:48:35 -04:00
David Holmes
10afc2dfd2 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
Reviewed-by: kvn, coleenp, dcubed
2015-08-26 18:59:08 -04:00
Dmitry Samersoff
6758393ebd Merge 2015-08-17 12:43:45 +03:00
Andrew Dinn
96413b5dac 8078743: AARCH64: Extend use of stlr to cater for volatile object stores
The current use of stlr on AArch64 to implement volatile stores needs to be extended to cater for object stores.

Reviewed-by: kvn, aph, enevill
2015-08-11 10:25:24 -04:00
Ed Nevill
4f5be2ee49 8133352: aarch64: generates constrained unpredictable instructions
Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt

Reviewed-by: kvn, aph, adinn
2015-08-18 12:40:22 +00:00
Ed Nevill
1c9f1ea099 8133935: aarch64: fails to build from source
Add inlucde of oops/oop.inline.hpp to fix build

Reviewed-by: coleenp
2015-08-19 11:59:02 +00:00
Zoltan Majo
1e55e60cb1 8076373: In 32-bit VM interpreter and compiled code process NaN values differently
Change interpreter to use XMM registers on x86_32 if they are available. Add stubs for methods transforming from/to int/long float/double.

Reviewed-by: kvn, mcberg
2015-08-19 08:55:18 +02:00
Aleksey Shipilev
f6c7ab6565 8131682: C1 should use multibyte nops everywhere
Reviewed-by: dlong, goetz, adinn, aph, vlivanov
2015-08-11 12:24:26 +03:00
Rickard Bäckman
21f9e19316 Merge 2015-08-06 16:28:08 +00:00
Andrew Dinn
bdc4e4d045 8132875: AArch64: Fix error introduced into AArch64 CodeCache by commit for 8130309
The fix for issue 8130309 introduced several errors into the AArch64 codecache routines

Reviewed-by: aph, thartmann, kvn
2015-08-03 05:05:40 -04:00
Jiangli Zhou
747d91708c Merge 2015-07-31 16:00:26 -04:00
Goetz Lindenmaier
fdbe749d2a 8132242: LogTouchedMethods (8025692) asserts if TieredCompilation is off
LogTouchedMethods causes the template interpreter to generate profiling code even if no compiler is used. If TieredCompilation is off, code containing an assertion that checks that UseCompiler is set, is reached. This assertion exists on the sparc and ppc platforms.

Reviewed-by: simonis, iklam, minqi
2015-07-29 15:08:42 -07:00
Roland Westrelin
51ddedd5c7 Merge 2015-07-23 19:11:28 +02:00